PC87366 datasheet(72/240 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.16 ACCESS.BUS INTERFACE (ACB) CONFIGURATION

2.16.1

General Description

The ACB is a two-wire synchronous serial interface compatible with the ACCESS.bus physical layer. The ACB uses a 24

MHz internal clock.

The six runtime registers are shown below.

Table 29. ACB Runtime Registers

2.16.2

Logical Device 8 (ACB) Configuration

Table 30 lists the configuration registers which affect the ACB. Only the last register (F0h) is described here. See Sections

2.2.3 and 2.2.4 for a detailed description of the others.

Table 30. ACB Conﬁguration Registers

Offset Mnemonic

Type

00h

ACBSDA

ACB Serial Data

R/W

01h

ACBST

ACB Status

Varies per bit

02h

ACBCST

ACB Control Status

Varies per bit

03h

ACBCTL1

ACB Control 1

R/W

04h

ACBADDR ACB Own Address

R/W

05h

ACBCTL2

ACB Control 2

R/W

Index

Conﬁguration Register or Action

Type

Reset

30h

Activate. See also bit 0 of the SIOCF1 register.

R/W

00h

60h

Base Address MSB register

R/W

00h

61h

Base Address LSB register. Bits 2-0 (for A2-0) are read only, 000b.

R/W

00h

70h

Interrupt Number and Wake-Up on IRQ Enable register

R/W

00h

71h

Interrupt Type. Bit 1 is read/write. Other bits are read only.

R/W

03h

74h

Report no DMA assignment

04h

75h

Report no DMA assignment

04h

F0h

ACB Conﬁguration register

R/W

00h

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