Specification
NET2272 USB Peripheral Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
61
8.4.12 (Address 24h; LOCCTL1) Local Bus Control Register 1
Bits
Description
Read
Write
Default
Value
7:3
Reserved
Yes
No
0
2
DMA DACK Enable. When clear, the NET2272 does not recognize the DACK
input pin. When set, the DACK input pin is enabled. This bit is automatically set
when the DMA Request Enable bit in the DMAREQ register is set. In split DMA
mode, this bit should not be cleared if there is a possibility that DACK will be
asserted.
Yes
Yes
0
1:0
DMA Mode.
This field determines the behavior of DREQ during DMA
transactions.
Value
Description
00
Slow DREQ. DREQ is de-asserted several clock periods after the start of
a DMA transaction, and is re-asserted several clock periods after the end of
the DMA transactions. This mode is compatible with the Net2270.
01
Fast DREQ. DREQ is de-asserted at the beginning of a DMA transaction,
and is re-asserted soon after the end of the DMA transaction. This mode
provides higher DMA performance.
10
Burst Mode. DREQ is asserted when the DMA Request Enable bit is set
and there is space/data available in the endpoint buffer. DREQ remains
asserted until either the buffer becomes empty/full,
the DMA Request
Enable bit is cleared, EOT is asserted, or EP_TRANSFER counts to 0 for
an IN endpoint.
11
Reserved.
Yes
Yes
0
8.4.13 (Address 25h; CHIPREV_2272) Net2272 Silicon Revision Register
Bits
Description
Read
Write
Default
Value
7:0
Chip Revision. This register returns the Net2272 silicon revision number.
Yes
No
‘h11
Note: The chip revision is encoded as a 2-digit BCD value. The most significant digit is the major revision number,
and the least significant digit is the minor revision number.
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