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STLC1502 Datasheet(PDF) 33 Page - STMicroelectronics |
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STLC1502 Datasheet(HTML) 33 Page - STMicroelectronics |
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33 / 81 page  33/81 STLC1502 Figure 10: Timer block diagram The timer clock is generated by a prescale unit. The timer clock may be one of: • The CKTIMER • The CKTIMER divided by 16, generated by 4 bits of prescale • the CKTIMER divided by 256, generated by a total of 8 bits of prescale Figure 11: Pre-scaler block diagram Using the recommended 2.208Mhz clock, the minimum interval between two timer interrupt is 452nsec (corre- sponding to the 2.208Mhz period) while the maximum interval between two timer interrupt is around 6sec. 7.1.3 Timer register map [0x0C000000] The base address of the timer register is 0x0C000000 Terminal Count Interrupt Value Load Control Timer Clock 16-bit Down Counter Load Register Control Register Divide by 16 CKTIMER Prescale Select Divide by 16 Timer Clock |
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