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M32C/86 Datasheet(PDF) 151 Page - Renesas Technology Corp

Part # M32C/86
Description  RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES
PDF  505 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M32C/86 Datasheet(HTML) 151 Page - Renesas Technology Corp

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Page 128
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13. DMAC
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Setting Value
DMA Request Source
b4 b3 b2 b1 b0
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
DMA0
Falling Edge of INT0
Both Edges of INT0
DMA1
DMA2
Falling Edge of INT2
Both Edges of INT2
DMA3
Falling Edge of INT3(1)
Both Edges of INT3(1)
Software trigger
Timer A0 Interrupt Request
Timer A1 Interrupt Request
Timer A2 Interrupt Request
Timer A3 Interrupt Request
Timer A4 Interrupt Request
Timer B0 Interrupt Request
Timer B1 Interrupt Request
Timer B2 Interrupt Request
Timer B3 Interrupt Request
Timer B4 Interrupt Request
Timer B5 Interrupt Request
UART0 Transmit Interrupt Request
UART0 Receive or ACK Interrupt Request(3)
UART1 Transmit Interrupt Request
UART1 Receive or ACK Interrupt Request(3)
UART2 Transmit Interrupt Request
UART2 Receive or ACK Interrupt Request(3)
UART3 Transmit Interrupt Request
UART3 Receive or ACK Interrupt Request(3)
UART4 Transmit Interrupt Request
UART4 Receive or ACK Interrupt Request(3)
Falling Edge of INT1
Both Edges of INT1
Intelligent I/O
Interrupt 0 Request(6)
Intelligent I/O
Interrupt 1 Request(7)
Intelligent I/O
Interrupt 2 Request
Intelligent I/O
Interrupt 3 Request
Intelligent I/O
Interrupt 4 Request
CAN Interrupt 5
Request
Intelligent I/O
Interrupt 8 Request
Intelligent I/O
Interrupt 9 Request(4)
Intelligent I/O
Interrupt 10 Request(5)
CAN Interrupt 2
Request
Intelligent I/O
Interrupt 0 Request(6)
Intelligent I/O
Interrupt 1 Request(7)
Intelligent I/O
Interrupt 2 Request
Intelligent I/O
Interrupt 3 Request
Intelligent I/O
Interrupt 4 Request
CAN Interrupt 5
Request
Intelligent I/O
Interrupt 9 Request(4)
Intelligent I/O
Interrupt 10 Request(5)
CAN Interrupt 2
Request
Intelligent I/O
Interrupt 0 Request(6)
Intelligent I/O
Interrupt 1 Request(7)
Intelligent I/O
Interrupt 2 Request
Intelligent I/O
Interrupt 3 Request
(Note 2)
(Note 2)
NOTES:
1. If the INT3 pin is used for data bus in memory expansion mode or microprocessor mode, a DMA3 interrupt request
cannot be generated by a signal applied to the INT3 pin.
2. The falling edge and both edges of signals applied to the INTj pin (j=0 to 3) cause a DMA request generation. The
INT interrupt (the POL bit in the INTjlC register, the LVS bit, the IFSR register) is not affected and vice versa.
3. Use the UkSMR register and UkSMR2 register (k=0 to 4) to switch between the UARTk receive and ACK interrupt
as a DMA request source.
To use the ACK interrupt for a DMA reqest, set the IICM bit in the UkSMR register to "1" and the IICM2 bit in the
UkSMR2 register to "0".
4. The same setting is used to generate an intelligent I/O interrupt 9 request and a CAN interrupt 0 request.
5. The same setting is used to generate an intelligent I/O interrupt 10 request and a CAN interrupt 1 request.
6. The same setting is used to generate an intelligent I/O interrupt 0 request and a CAN interrupt 3 request.
7. The same setting is used to generate an intelligent I/O interrupt 1 request and a CAN interrupt 4 request.
A/D0 Interrupt Request
Intelligent I/O
Interrupt 8 Request
Table 13.2 DMiSL Register (i = 0 to 3) Function



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