D950-CORE datasheet(7/89 Pages) STMICROELECTRONICS

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D950-Core

Table 2.2

PROGRAM BUS (35 PINS)

Table 2.3

BUS CONTROL (3 PINS)

Table 2.4

GENERAL PURPOSE P-PORT (9 PINS)

Table 2.5

CLOCK (4 PINS)

Pin Name

Type

Description

ID0-ID15

I/O

Instruction data bus.

Hi-Z during cycles with no I-bus exchange.

IA0-IA15

Instruction address bus.

Hi-Z when in Hold.

IRD

I-bus read strobe. Active low.

Hi-Z when in Hold.

IWR

I-bus write strobe. Active low.

Hi-Z when in Hold.

IBS

I-bus strobe. Active low.

Hi-Z in Hold.

Asserted low at the beginning of a valid I-bus cycle.

Pin Name

Type

Description

DTACK

Data transfer acknowledge. Active low.

Sampled on CLKIN rising edge.

Controls bus cycle extension by insertion of wait-states.

HOLD

Hold bus request signal. Active low.

Asserted by a peripheral (DMA controller) requiring bus mastership. Halts

program execution and tri-states buses.

HOLDACK

Hold Acknowledge output. Active low. Indicates that all buses are in Hi-Z.

Pin Name

Type

Description

P0-P7

I/O

8-bit bidirectional parallel port. Each pin can be individually programmed as

input or output and as level or falling edge sensitive input conditions for test

by branch and conditional instructions.

P_EN

Direction of Port

Pin Name

Type

Description

CLKIN

Clock input.

CLK_EMU

Emulation Clock input

DMA_CLK

DMA Clock output

BSU_CLK

BSU Clock output

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