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D950-CORE Datasheet(PDF) 8 Page - STMicroelectronics

Part # D950-CORE
Description  16-Bit Fixed Point Digital Signal Processor DSP Core
PDF  89 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

D950-CORE Datasheet(HTML) 8 Page - STMicroelectronics

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D950-Core
Table 2.6
CONTROL (13 PINS)
Pin Name
Type
Description
IT
I
Maskable Interrupt Request Input. Falling edge sensitive.
ITACK
O
Maskable Interrupt Request Acknowledge. Active Low.
Asserted low at the beginning of Interrupt servicing.
EOI
O
End of maskable Interrupt routine output. Active low.
Asserted low at the end of current interrupt request processing.
LP
I
Low power. Falling edge sensitive.
Stops the processor after execution of the currently decoded instruction and
enters low-power standby state (in this state, the clock generator is stopped
except for INCYCLE).
LPACK
O
Low power Acknowledge. Active low.
Asserted low at the end of execution of the last instruction following detec-
tion of LP falling edge or at the end of LP or STOP instruction.
RESET
I
Reset input. Active low.
Initializes the processor to the RESET state and the clock generator. Forces
Program Counter value to reset address and execution of NOP instruction.
MODE
I
Mode input select.
Forces reset address to 0x0000 (resp. 0xFC00) when low (resp. high).
VCI
O
Valid co-processor instruction decoded.
Asserted high while decoding a co-processor dedicated instruction. Indi-
cates that the co-processor instruction will be executed at the following in-
struction cycle.
IRD_WR
O
Indicates program memory RD/WR cycle during execution of Read or Write
Program memory instruction.
INCYCLE
O
Instruction cycle. Asserted high at the beginning of cycle.
RESET_OUT
O
Hardware and Software Reset Output
STACKX
O
X Stack read/write instruction
STACKY
O
Y Stack read/write instruction
3



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