ADE75 datasheet(144/148 Pages) AD

144 / 148 page

ADE75xx/ADE71xx

Preliminary Technical Data

Rev. PrE | Page 144 of 148

GPIO

BCTRL

INT1 input disabled

INT1 input enabled

Controls the function of INT0

INT0PRG

Function

INT0 input disabled

INT0PRG

INT0 input enabled

Table 147.Table 148. Port 0 Alternate Functions

No.

Alternate Function

Alternate Function Enable

BCTRL external battery control input

Set INT1PROG[2:0]=X01 in the Interrupt pins configuration

SFR (INTPR, 0xFF)

INT1 external interrupt

Set EX1 in the Interrupt Enable SFR (IE, 0xA8).

P0.0

INT1 wakeup from PSM2 operating mode

Set INT1PROG[2:0]=11X in the Interrupt pins configuration

SFR (INTPR, 0xFF)

P0.1

FP19 LCD Segment Pin

Set FP19EN in the LCD Segment Enable 2 SFR (LCDSEGE2,

0xED)

CF1 ADE Calibration Frequency output

Clear the DISCF1 bit in the ADE energy measurement

internal MODE1 register (0x0B)

RTC Calibration output

Select the calibration window and frequency options and

then set the RTCCAL bit in the Interrupt pins configuration

SFR (INTPR, 0xFF)

P0.2

Note: The RTC Calibration output has priority over the CF1 output, so if the DISCF1 in the MODE1 register

(0x0B) is clear and RTCCAL bit in the Interrupt pins configuration SFR (INTPR, 0xFF) is set, the P0.2/CF1/RTCCAL

pin will follow the RTC Calibration output.

P0.2

CF1 ADE Calibration Frequency output

Clear the DISCF1 bit in the ADE energy measurement

internal MODE1 register (0x0B)

P0.3

CF2 ADE Calibration Frequency output

Clear the DISCF2 bit in the ADE energy measurement

internal MODE1 register (0x0B)

MOSI SPI Data line

Set the SCPS bit in the CFG SFR and set the SPIEN bit in the

SPI Configuration Register SFR (SPIMOD1, 0xE8).

P0.4

SDATA I2C Data line

Clear the SCPS bit in the Configuration SFR (CFG, 0xAF) and

set the I2CEN bit in the I2C Mode Register SFR (I2CMOD,

0xE8).

P0.5

MISO SPI Data line

Set the SCPS bit in the Configuration SFR (CFG, 0xAF) and set

the SPIEN bit in the SPI Configuration Register SFR

(SPIMOD2, 0xE9)

SCLK serial clock for I2C or SPI

Set the I2CEN bit in the I2CMOD SFR or the SPIEN bit in the

SPI Configuration Register SFR (SPIMOD2, 0xE9) to enable

the I2C or SPI interface

P0.6

T0 Timer0 input

Set the CNT0 bit in the Timer/Counter 0 and 1 Mode SFR

(TMOD, 0x89) to enable T0 as an external event counter

SS SPI slave select input for SPI in slave mode

Set the SS_EN bit in the SPI Configuration Register SFR

(SPIMOD1, 0xE8)

SS SPI slave select output for SPI in master

mode

Set the SPIMS_b bit in the SPI Configuration Register SFR

(SPIMOD2, 0xE9)

P0.7

T1 Timer 1 input

Set the CNT1 bit in the Timer/Counter 0 and 1 Mode SFR

(TMOD, 0x89) to enable T1 as an external event counter

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