ADE75 datasheet(145/148 Pages) AD

145 / 148 page

Preliminary Technical Data

ADE75xx/ADE71xx

Rev. PrE | Page 145 of 148

Table 149. Port 1 Alternate Functions

No.

Alternate Function

Alternate Function Enable

RxD Receiver Data Input for UART

Set the REN bit in the SCON SFR Bit Description SFR (SCON,

0x98).

P1.0

RX Edge wakeup from PSM2 operating mode

Set RXPROG[1:0]=11 in the Peripheral Configuration SFR

(PERIPH, 0xF4)

P1.1

TxD Transmitter Data Output for UART

P1.2

FP25 LCD Segment Pin

Set FP25EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)

FP24 LCD Segment Pin

Set FP24EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)

P1.3

T2EX Timer 2 control input

Set EXEN2 in the Timer/Counter 2 Control SFR (T2CON, 0xC8)

FP23 LCD Segment Pin

Set FP23EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)

P1.4

T2 Timer 2 input

Set the CNT2 bit in the Timer/Counter 2 Control SFR (T2CON,

0xC8) to enable T2 as an external event counter

P1.5

FP22 LCD Segment Pin

Set FP22EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)

P1.6

FP21 LCD Segment Pin

Set FP21EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)

P1.7

FP20 LCD Segment Pin

Set FP20EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)

Table 150. Port 2 Alternate Functions

No.

Alternate Function

Alternate Function Enable

P2.0

FP18 LCD Segment Pin

Set FP18EN in the LCD Segment Enable 2 SFR (LCDSEGE2,

0xED)

P2.1

FP17 LCD Segment Pin

Set FP17EN in the LCD Segment Enable 2 SFR (LCDSEGE2,

0xED)

P2.2

FP16 LCD Segment Pin

Set FP16EN in the LCD Segment Enable 2 SFR (LCDSEGE2,

0xED)

P2.3

SDEN Serial Download pin sampled on reset.

P2.3 is an output only.

Enabled by default.

PORT 0

Port 0 is controlled directly through the bit-addressable Port 0 SFR (80H). The weak internal pull-ups for Port 0 are configured through

the Port 0 Weak pull-up enable SFR (PINMAP0, 0xB2); they are enabled by default. Disable the weak internal pull-up by writing a one to

P0CFG..x.

Port 0 pins also have various secondary functions as described in Interrupt pins configuration SFR (INTPR, 0xFF)

Bit

Location

Bit

Mnemonic

Default

Value

Description

RTCCAL

Control RTC calibration output

When set, the RTC calibration frequency selected by FSEL[1:0] is

output on the P0.2/CF1/RTCCAL pin.

Sets RTC calibration output frequency and calibration window

FSEL[1:0]

Calibration window, frequency

30.5 seconds, 1Hz

30.5 seconds, 512 Hz

0.244 seconds, 500Hz

6-5

FSEL[1:0]

0.244 seconds, 16.384 kHz

Reserved

Controls the function of T

INT1PRG[2:0]

Function

3-1

INT1PRG[2:0]

000

GPIO

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