L99VR02XP datasheet(48/50 Pages) STMICROELECTRONICS

48 / 50 page

List of figures

Figure 1.

Functional block diagram ............................................................. 3

Figure 2.

Pins configuration (top view)........................................................... 4

Figure 3.

Rth_amb junction to ambient thermal resistance .............................................. 7

Figure 4.

Output voltage vs TJ ............................................................... 16

Figure 5.

Output voltage vs VS_LDO1,2 .......................................................... 16

Figure 6.

Drop voltage vs output current ........................................................ 16

Figure 7.

Current consumption vs output current .................................................. 16

Figure 8.

Current consumption vs input voltage (IO < 1 mA) ........................................... 16

Figure 9.

Current consumption vs input voltage (IO = 50 mA) .......................................... 16

Figure 10.

Current consumption vs input voltage (IO = 150 mA) ......................................... 17

Figure 11.

Short circuit current vs TJ (Ishort pin tied to GND)............................................ 17

Figure 12.

Short-circuit current vs TJ (Ishort pin floating)............................................... 17

Figure 13.

Short-circuit current vs input voltage .................................................... 17

Figure 14.

Output voltage vs enable voltage (VO_LDO1,2 = 0.8 V) ........................................ 17

Figure 15.

Output voltage vs enable voltage (VO_LDO1,2 = 1.2 V) ........................................ 17

Figure 16.

Output voltage vs enable voltage (VO_LDO1,2 = 1.5 V) ........................................ 18

Figure 17.

Output voltage vs enable voltage (VO_LDO1,2 = 1.8 V) ........................................ 18

Figure 18.

Output voltage vs enable voltage (VO_LDO1,2 = 2.5 V) ........................................ 18

Figure 19.

Output voltage vs enable voltage (VO_LDO1,2 = 2.8 V) ........................................ 18

Figure 20.

Output voltage vs enable voltage (VO_LDO1,2 = 3.3 V) ........................................ 18

Figure 21.

Output voltage vs enable voltage (VO_LDO1,2 = 5 V).......................................... 18

Figure 22.

VEN_high_LDO1,2 vs TJ .............................................................. 18

Figure 23.

VEN_low_LDO1,2 vs TJ ............................................................... 18

Figure 24.

Vwhth_LDO1,2 vs TJ................................................................. 19

Figure 25.

Vwlth_LDO1,2 vs TJ ................................................................. 19

Figure 26.

ICWc_LDO1,2 vs TJ ................................................................. 19

Figure 27.

ICWd_LDO1,2 vs TJ ................................................................. 19

Figure 28.

Icr_LDO1,2 vs TJ ................................................................... 19

Figure 29.

Twop vs TJ ...................................................................... 19

Figure 30.

ISELx_LDO1,2 vs VS_LDO1,2 ........................................................... 20

Figure 31.

Vtrk vs temperature (VO_LDO1,2 = 5 V, 3.3 V, 2.8 V, 2.5 V, 1.8 V) ................................. 20

Figure 32.

Vtrk vs temperature (VO_LDO1,2 = 1.5 V, 1.2 V, 0.8 V) ......................................... 20

Figure 33.

PSRR ......................................................................... 20

Figure 34.

Load regulation test circuit ........................................................... 21

Figure 35.

Maximum load variation response (5 V) .................................................. 21

Figure 36.

Maximum load variation response (3.3 V)................................................. 21

Figure 37.

Application schematic - Single rail line, dual outputs ......................................... 22

Figure 38.

Application schematic - Dual rail input lines, dual outputs ...................................... 22

Figure 39.

Application schematic - Dual rail input lines, post regulation .................................... 22

Figure 40.

Behavior of regulated voltage VO_LDO1,2 versus output current .................................. 23

Figure 41.

Ishort versus Rsh .................................................................. 24

Figure 42.

Example of output voltage selection .................................................... 25

Figure 43.

Typical example of enable control ...................................................... 25

Figure 44.

Reset timing diagram............................................................... 26

Figure 45.

Watchdog timing diagram............................................................ 27

Figure 46.

Thermal warning diagram............................................................ 28

Figure 47.

Thermal clusters identification......................................................... 29

Figure 48.

Square ware on TW_LDO1,2 pins generated during an overvoltage .............................. 30

Figure 49.

Warning signal caused by overvoltage and thermal warning on TW_LDO1,2 pins ..................... 30

Figure 50.

Finite state machine ............................................................... 32

L99VR02XP

List of figures

DS14686 - Rev 1

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