DSP56362P datasheet(78/152 Pages) FREESCALE

78 / 152 page

Serial Host Interface SPI Protocol Timing

DSP56362 Technical Data, Rev. 4

3-52

Freescale Semiconductor

Figure 3-33 Host DMA Read Timing Diagram

3.12

Serial Host Interface SPI Protocol Timing

Table 3-21 Serial Host Interface SPI Protocol Timing

No.

Characteristics

Mode

Filter Mode

Expression

100MHz

Unit

Min

Max

140

Tolerable spike width on clock or data in

—

Bypassed

Narrow

Wide

——

—

100

141

Minimum serial clock cycle = tSPICC(min)

Master

Bypassed

Narrow

Wide

×T

C+46

×T

C+152

×T

C+223

106

212

283

—

142

Serial clock high period

Master

Bypassed

Narrow

Wide

0.5

×t

SPICC –10

0.5

×t

SPICC –10

0.5

×t

SPICC –10

131

—

Slave

Bypassed

Narrow

Wide

2.5

×T

C+12

2.5

×T

C+102

2.5

×T

C+189

127

214

—

143

Serial clock low period

Master

Bypassed

Narrow

Wide

0.5

×t

SPICC –10

0.5

×t

SPICC –10

0.5

×t

SPICC –10

131

—

Slave

Bypassed

Narrow

Wide

2.5

×T

C+12

2.5

×T

C+102

2.5

×T

C+189

127

214

—

326

317

318

327

328

329

Data

Valid

HOREQ

(Output)

HACK

(Input)

H0-H7

(Output)

RXH

Read

343

342

DSP56362P Datasheet(PDF) 78 Page - Freescale Semiconductor, Inc

DSP56362P Datasheet(HTML) 78 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL