SH7708 datasheet(133/633 Pages) RENESAS

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6.3

INTC Registers

6.3.1

Interrupt Priority Registers A and B (IPRA, IPRB)

Interrupt priority registers A and B (IPRA and IPRB) are 16-bit read/write registers that set

priority levels from 0 to 15 for on-chip supporting module interrupts. These registers are

initialized to H'0000 by a reset. They are not initialized in standby mode.

Bit:

Bit name:

Initial value:

R/W:

R/W

Bit:

Bit name:

Initial value:

R/W:

R/W

Table 6.5 lists the relationship between the interrupt sources and the IPRA and IPRB bits.

Table 6.5

Interrupt Request Sources and IPRA, IPRB

Bits 15 to 12

Bits 11 to 8

Bits 7 to 4

Bits 3 to 0

IPRA

TMU0

TMU1

TMU2

RTC

IPRB

WDT

REF*1

SCI

Reserved *2

Notes: 1. REF is the memory refresh unit in the bus state controller. See section 10, Bus State

Controller, for details.

2. Reserved bits: Always read 0. Only 0 should be written.

As listed in table 6.5, four sets of on-chip supporting modules are assigned to each register. 4-bit

groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) are set with values from H'0 (0000)

to H'F (1111). Setting H'0 means priority level 0 (masking is requested); H'F is priority level 15

(the highest level).

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