LAN91C100FD datasheet(24/79 Pages) SMSC

24 / 79 page

FEAST Fast Ethernet Controller with Full Duplex Capability

Rev. 10/14/2002

Page 24

SMSC DS – LAN91C100FD Rev. D

PRELIMINARY

LOOP - Loopback. General purpose output port used to control the LBK pin. Typically used to put the PHY

chip in loopback mode.

TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared the

LAN91C100FD will complete the current transmission before stopping. When stopping due to an error, this

bit is automatically cleared.

BANK 0

OFFSET

NAME

TYPE

SYMBOL

EPH STATUS REGISTER

READ ONLY

EPHSR

This register stores the status of the last transmitted frame. This register value, upon individual transmit

packet completion, is stored as the first word in the memory area allocated to the packet. Packet interrupt

processing should use the copy in memory as the register itself will be updated by subsequent packet

transmissions. The register can be used for real time values (like TXENA and LINK OK). If TXENA is

cleared the register holds the last packet completion status.

HIGH

BYTE

UNRN

LINK_

CTR

_ROL

EXC

_DEF

LOST

CARR

LATCOL

-nLNK

LOW

BYTE

DEFR

LTX

BRD

SQET

16COL

LTX

MULT

MUL

COL

SNGL

COL

TX_SUC

TXUNRN - Transmit Under Run. Set if under run occurs, it also clears TXENA bit in TCR. Cleared by

setting TXENA high. This bit may only be set if early TX is being used.

LINK_OK - General purpose input port driven by nLNK pin inverted. Typically used for Link Test. A

transition on the value of this bit generates an interrupt.

CTR_ROL - Counter Roll Over. When set one or more 4 bit counters have reached maximum count (15).

Cleared by reading the ECR register.

EXC_DEF - Excessive Deferral. When set last/ current transmit was deferred for more than 1518 * 2 byte

times. Cleared at the end of every packet sent.

LOST_CARR - Lost Carrier Sense. When set indicates that Carrier Sense was not present at end of

preamble. Valid only if MON_CSN is enabled. This condition causes TXENA bit in TCR to be reset.

Cleared by setting TXENA bit in TCR.

LATCOL - Late collision detected on last transmit frame. If set a late collision was detected (later than 64

byte times into the frame). When detected the transmitter jams and turns itself off clearing the TXENA bit

in TCR. Cleared by setting TXENA in TCR.

TX_DEFR - Transmit Deferred. When set, carrier was detected during the first 6.4

µs of the inter frame

gap. Cleared at the end of every packet sent.

LTX_BRD - Last transmit frame was a broadcast. Set if frame was broadcast. Cleared at the start of every

transmit frame.

SQET - Signal Quality Error Test. In MII, SQET bit is always set after first transmit, except if SWFDUP=1.

As a consequence, the STP_SQET bit in the TCR register cannot be set as it will always result in transmit

fatal error. In non-MII systems, the transmitter opens a 1.6

µs window 0.8 µs after transmission is

completed and the receiver returns inactive. During this window, the transmitter expects to see the SQET

signal from the transceiver. The absence of this signal is a 'Signal Quality Error' and is reported in this

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