LAN91C100FD datasheet(44/79 Pages) SMSC

44 / 79 page

FEAST Fast Ethernet Controller with Full Duplex Capability

Rev. 10/14/2002

Page 44

SMSC DS – LAN91C100FD Rev. D

PRELIMINARY

5.4

Typical Flow of Events for Receive

S/W DRIVER

MAC SIDE

1 ENABLE RECEPTION - By setting the RXEN

bit.

A packet is received with matching address.

Memory is requested from MMU. A packet

number is assigned to it. Additional memory is

requested if more pages are needed.

The internal DMA logic generates sequential

addresses and writes the receive words into

memory. The MMU does the sequential to

physical address translation. If overrun, packet

is dropped and memory is released.

When the end of packet is detected, the status

word is placed at the beginning of the receive

packet in memory. Byte count is placed at the

second word. If the CRC checks correctly the

packet number is written into the RX FIFO. The

RX FIFO, being not empty, causes RCV INT

(interrupt) to be set. If CRC is incorrect the

packet memory is released and no interrupt will

occur.

5 SERVICE INTERRUPT - Read the Interrupt

Status Register and determine if RCV INT is set.

The next receive packet is at receive area. (Its

packet number can be read from the FIFO Ports

packet by accessing the RX area, and can move

it out to system memory if desired. When

processing is complete the CPU issues the

REMOVE AND RELEASE FROM TOP OF RX

command to have the MMU free up the used

memory and packet number.

LAN91C100FD Datasheet(PDF) 44 Page - SMSC Corporation