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LAN91C100FD Datasheet(PDF) 79 Page - SMSC Corporation |
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LAN91C100FD Datasheet(HTML) 79 Page - SMSC Corporation |
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79 / 79 page ![]() FEAST Fast Ethernet Controller with Full Duplex Capability SMSC DS – LAN91C100FD Rev. D Page 79 Rev. 10/14/2002 PRELIMINARY Chapter 11 LAN91C100FD REV. D Revisions PAGE(S) SECTION/FIGURE/ENTRY CORRECTION DATE REVISED 23 Bank 0 Offset 0—Transmit Control Register Modified the description of the FDUPLX bit and the PAD_EN bit 09/01/02 30 Bank 2 Offset C—Interrupt Status Register Modified the description of the Interrupt Register bits 09/01/02 37 Figure 5.2 - Interrupt Structure Modified the interrupt structure figure 09/01/02 41 Typical Flow of Events for Transmit (Auto Release = 0) Modified the Transmit Flow Routine 09/01/02 77 Figure 10.1 - 208 Pin QFP Package Outline Modified the package outlines 09/01/02 78 Figure 10.2 - 208 Pin TQFP Package Outlines Modified the package outlines 09/01/02 65 Removed Application Note Removed: Alliance AS7C256-15, Hyundai HY638256- LJ15, Winbond 24257AJ-12, Cypress CY7C199-12VC, Cypress CYC199-15VC 10/13/00 64 Operational Description Supply Current Active Parameter - Changed Icc Type to 25 ma and Max Icc to 40 ma. Icsby (Standby current) deleted. 06/27/00 7 Description of Pin Functions Pin 175 – Changed to active high signal. 06/01/00 24 Table under Bank 0 Changed RX_OVRN to 0 on High Byte row. Removed references to RX_OVRN under table. 06/01/00 74 DC Electrical and Timing Section Updated SRAM Interface Timing information. Added additional timing parameters. 01/28/00 64 Operational Description Supply Current Active Parameter - Changed Icc Type to 25 ma and Max Icc to 40 ma. Icsby (Standby current) deleted. 06/27/00 7 Operational DescriptionDescription of Pin Functions Pin 175 – Changed to active high signal. 06/01/00 23 Table under Bank 0 Changed RX_OVRN to 0 on High Byte row. Removed references to RX_OVRN under table. 06/01/00 74 DC Electrical and Timing Section Updated SRAM Interface Timing information. Added additional timing parameters. 01/28/00 |
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