LAN91C100FD datasheet(61/79 Pages) SMSC

61 / 79 page

FEAST Fast Ethernet Controller with Full Duplex Capability

SMSC DS – LAN91C100FD Rev. D

Page 61

Rev. 10/14/2002

PRELIMINARY

7.4

EISA 32 Bit SLAVEEISA 32 Bit Slave

On EISA the LAN91C100FD is accessed as a 32 bit I/O slave, along with a Slave DMA type "C" data path

option. As an I/O slave, the LAN91C100FD uses asynchronous accesses. In creating nRD and nWR

inputs, the timing information is externally derived from nCMD edges. Given that the access will be at least

1.5 to 2 clocks (more than 180ns at least) there is no need to negate EXRDY, simplifying the EISA

interface implementation. As a DMA Slave, the LAN91C100FD accepts burst transfers and is able to

sustain the peak rate of one doubleword every BCLK. Doubleword alignment is assumed for DMA

transfers. Up to three extra bytes in the beginning and at the end of the transfer should be moved by the

CPU using I/O accesses to the Data Register. The LAN91C100FD will sample EXRDY and postpone DMA

cycles if the memory cycle solicits wait states.

Table 7.3 - EISA 32 Bit Slave Signal Connections

EISA BUS

SIGNAL

LAN91C100FD

SIGNAL

NOTES

LA2-LA15

A2-A15

Address bus used for I/O space and register decoding,

latched by nADS (nSTART) trailing edge.

M/nIO

AEN

Qualifies valid I/O decoding - enabled access when low.

These signals are externally ORed. Internally the AEN pin is

latched by nADS rising edge and transparent while nADS is

low.

Latched W-R

combined with

nCMD

nRD

I/O Read strobe - asynchronous read accesses. Address is

valid before its leading edge. Must not be active during DMA

bursts if DMA is supported.

Latched W-R

combined with

nCMD

nWR

I/O Write strobe - asynchronous write access. Address is

valid before leading edge . Data latched on trailing edge.

Must not be active during DMA bursts if DMA is supported.

nSTART

nADS

Address strobe is connected to EISA nSTART.

RESDRV

RESET

nBE0 nBE1

nBE2 nBE3

nBE0 n BE1

nBE2 nBE3

Byte enables. Latched on nADS rising edge.

IRQn

INTR0-INTR3

Interrupts used as active high edge triggered

D0-D31

32 bit data bus. The bus byte(s) used to access the device

are a function of nBE0-nBE3:

nBE0

nBE1 nBE2

nBE3

Double word access

Low word access

High word access

Byte 0 access

Byte 1 access

Byte 2 access

Byte 3 access

Not used = tri-state on reads, ignored on writes. Note that

nBE2 and nBE3 override the value of A1, which is tied low in

this application. Other combinations of nBE are not

supported by the LAN91C100FD. Software drivers are not

anticipated to generate them.

LAN91C100FD Datasheet(PDF) 61 Page - SMSC Corporation

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