LAN91C100FD datasheet(32/79 Pages) SMSC

32 / 79 page

FEAST Fast Ethernet Controller with Full Duplex Capability

Rev. 10/14/2002

Page 32

SMSC DS – LAN91C100FD Rev. D

PRELIMINARY

Notes:

Bits N2,N1,N0 bits are ignored by the LAN91C100FD but should be used for command 0 to preserve software

compatibility with the LAN91C92 and future devices. They should be zero for all other commands.

When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with

outstanding packets, or re-enqueuing them. Packet numbers in the completion FIFO can be read via the FIFO ports

MMU commands releasing memory (commands 4 and 5) should only be issued if the corresponding packet number

has memory allocated to it.

COMMAND SEQUENCING

A second allocate command (command 1) should not be issued until the present one has completed.

Completion is determined by reading the FAILED bit of the allocation result register or through the

allocation interrupt.

A second release command (commands 4, 5) should not be issued if the previous one is still being

processed. The BUSY bit indicates that a release command is in progress. After issuing command 5, the

contents of the PNR should not be changed until BUSY goes low. After issuing command 4, command 3

should not be issued until BUSY goes low.

BUSY BIT - Readable at bit 0 of the MMU command register address. When set indicates that MMU is still

processing a release command. When clear, MMU has already completed last release command. BUSY

and FAILED bits are set upon the trailing edge of command.

BANK 2

OFFSET

NAME

TYPE

SYMBOL

PACKET NUMBER REGISTER

READ/WRITE

PNR

PACKET NUMBER AT TX AREA

PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is

accessible through the TX area. Some MMU commands use the number stored in this register as the

packet number parameter. This register is cleared by a RESET or a RESET MMU Command.

OFFSET

NAME

TYPE

SYMBOL

ALLOCATION RESULT REGISTER

READ ONLY

ARR

This register is updated upon an ALLOCATE MEMORY MMU command.

FAILED

ALLOCATED PACKET NUMBER

FAILED - A zero indicates a successful allocation completion. If the allocation fails the bit is set and only

cleared when the pending allocation is satisfied. Defaults high upon reset and reset MMU command. For

polling purposes, the ALLOC_INT in the Interrupt Status Register should be used because it is

synchronized to the read operation. Sequence:

Allocate Command

Poll ALLOC_INT bit until set

Read Allocation Result Register

LAN91C100FD Datasheet(PDF) 32 Page - SMSC Corporation

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