LAN91C100FD datasheet(35/79 Pages) SMSC

35 / 79 page

FEAST Fast Ethernet Controller with Full Duplex Capability

SMSC DS – LAN91C100FD Rev. D

Page 35

Rev. 10/14/2002

PRELIMINARY

OFFSET

NAME

TYPE

SYMBOL

INTERRUPT ACKNOWLEDGE

WRITE ONLY

ACK

RX_DISC

INT

ERCV INT

RX_OVRN

INT

TX EMPTY

INT

TX INT

OFFSET

NAME

TYPE

SYMBOL

INTERRUPT MASK REGISTER

READ/WRITE

MSK

RX_DISC

INT

ERCV INT

EPH INT

RX_OVRN

INT

ALLOC

INT

TX EMPTY

INT

TX INT

RCV INT

This register can be read and written as a word or as two individual bytes.

The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low. A

MASK bit being set will cause a hardware interrupt.

Note:

The Bit 7 mask must never be written high (1).

RX_DISC INT - Set when the nRXDISC PIN COUNTER in the ERCV register increments to a value of FF.

The RX_DISC INT bit latches the condition for the purpose of being polled or generating an interrupt, and

will only be cleared by writing the acknowledge register with the RX_DISC INT bit set.

ERCV INT - Early receive interrupt. Set whenever a receive packet is being received, and the number of

bytes received into memory exceeds the value programmed as ERCV THRESHOLD (Bank 3, Offset Ch).

ERCV INT stays set until acknowledged by writing the INTERRUPT ACKNOWLEDGE REGISTER with the

ERCV INT bit set.

EPH INT - Set when the Ethernet Protocol Handler section indicates one out of various possible special

conditions. This bit merges exception type of interrupt sources, whose service time is not critical to the

execution speed of the low level drivers. The exact nature of the interrupt can be obtained from the EPH

Status Register (EPHSR), and enabling of these sources can be done via the Control Register. The

possible sources are:

LINK - Link Test transition

CTR_ROL - Statistics counter roll over

TXENA cleared - A fatal transmit error occurred forcing TXENA to be cleared. TX_SUC will be low

and the specific reason will be reflected by the bits:

3.1

TXUNRN - Transmit under-run

3.2

SQET - SQE Error

3.3

LOST CARR - Lost Carrier

3.4

LATCOL - Late Collision

3.5

16COL - 16 collisions

Any of the above interrupt sources can be masked by the appropriate ENABLE bits in the Control Register.

1) LE ENABLE (Link Error Enable), 2) CR ENABLE (Counter Roll Over), 3) TE ENABLE (Transmit Error

Enable)

EPH INT will only be cleared by the following methods:

LAN91C100FD Datasheet(PDF) 35 Page - SMSC Corporation

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