LAN91C100FD datasheet(4/79 Pages) SMSC

4 / 79 page

FEAST Fast Ethernet Controller with Full Duplex Capability

Rev. 10/14/2002

Page 4

SMSC DS – LAN91C100FD Rev. D

PRELIMINARY

Figure 5.7 - Drive Send and Allocate Routines ............................................................................................................49

Figure 5.8 - Interrupt Generation for Transmit, Receive, MMU ....................................................................................52

Figure 6.1 - 64 X 16 Serial EEPROM Map...................................................................................................................55

Figure 7.1 - LAN91C100FD on VL BUS.......................................................................................................................58

Figure 7.2 - LAN91C100FD on ISA Bus.......................................................................................................................60

Figure 7.3 - LAN91C100FD on EISA Bus ....................................................................................................................63

Figure 9.1 - Asynchronous Cycle - nADS=0.................................................................................................................67

Figure 9.2 - Asynchronous Cycle - Using nADS...........................................................................................................68

Figure 9.3 - Asynchronous Cycle - nADS=0.................................................................................................................69

Figure 9.4 - Burst Write Cycles - nVLBUS=1 ...............................................................................................................70

Figure 9.5 - Burst Read Cycles - nVLBUS=1 ...............................................................................................................71

Figure 9.6 - Address Latching for all Modes.................................................................................................................72

Figure 9.7 - Synchronous Write Cycles - nVLBUS=0...................................................................................................72

Figure 9.8 - Synchronous Read Cycle - NVLBUS=0....................................................................................................73

Figure 9.9 - SRAM Interface ........................................................................................................................................74

Figure 9.10 - ENDEC Interface - 10 Mbps ...................................................................................................................75

Figure 9.11 - MII Interface............................................................................................................................................76

Figure 10.1 - 208 Pin QFP Package Outline ................................................................................................................77

Figure 10.2 - 208 Pin TQFP Package Outlines ............................................................................................................78

LIST OF TABLES

Table 3.1 - LAN91C100FD Pin Requirements

Table 5.1 - Internal I/O Space Mapping

Table 7.1 - VL Local Bus Signal Connections

Table 7.2 - High-End ISA or Non-Burst EISA Machines Signal Connectors

Table 7.3 - EISA 32 Bit Slave Signal Connections

Table 10.1 - 208 Pin QFP Package Parameters

Table 10.2 - 208 Pin TQFP Package Outlines

LAN91C100FD Datasheet(PDF) 4 Page - SMSC Corporation

LAN91C100FD Datasheet(HTML) 4 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Datasheet Download

Link URL