LAN91C100FD datasheet(34/79 Pages) SMSC

34 / 79 page

FEAST Fast Ethernet Controller with Full Duplex Capability

Rev. 10/14/2002

Page 34

SMSC DS – LAN91C100FD Rev. D

PRELIMINARY

READ - Determines the type of access to follow. If the READ bit is high the operation intended is a read. If

the READ bit is low the operation is a write. Loading a new pointer value, with the READ bit high,

generates a pre-fetch into the Data Register for read purposes.

Readback of the pointer will indicate the value of the address last accessed by the CPU (rather than the

last pre-fetched). This allows any interrupt routine that uses the pointer, to save it and restore it without

affecting the process being interrupted. The Pointer Register should not be loaded until the Data Register FIFO is

empty. The NOT EMPTY bit of this register can be read to determine if the FIFO is empty. On reads, if IOCHRDY is

not connected to the host, the Data Register should not be read before 370ns after the pointer was loaded to allow the

Data Register FIFO to fill.

If the pointer is loaded using 8 bit writes, the low byte should be loaded first and the high byte last.

ETEN - When set enables EARLY Transmit underrun detection. Normal operation when clear.

NOT EMPTY - When set indicates that the Write Data FIFO is not empty yet. The CPU can verify that the

FIFO is empty before loading a new pointer value. This is a read only bit.

Note:

If AUTO INCR. is not set, the pointer must be loaded with a dword aligned value.

BANK 2

OFFSET

NAME

TYPE

SYMBOL

8 THROUGH BH

DATA REGISTER

READ/WRITE

DATA

DATA HIGH

DATA LOW

DATA REGISTER - Used to read or write the data buffer byte/word presently addressed by the pointer

This register is mapped into two uni-directional FIFOs that allow moving words to and from the

LAN91C100FD regardless of whether the pointer address is even, odd or dword aligned. Data goes

through the write FIFO into memory, and is pre-fetched from memory into the read FIFO. If byte accesses

are used, the appropriate (next) byte can be accessed through the Data Low or Data High registers. The

order to and from the FIFO is preserved. Byte, word and dword accesses can be mixed on the fly in any

order.

This register is mapped into two consecutive word locations to facilitate double word move operations

regardless of the actual bus width (16 or 32 bits). The DATA register is accessible at any address in the 8

through Ah range, while the number of bytes being transferred is determined by A1 and nBE0-nBE3. The

FIFOs are 12 bytes each.

BANK 2

OFFSET

NAME

TYPE

SYMBOL

INTERRUPT STATUS REGISTER

READ ONLY

IST

RX_DISC

INT

ERCV INT

EPH INT

RX_OVRN

INT

ALLOC

INT

TX EMPTY

INT

TX INT

RCV INT

LAN91C100FD Datasheet(PDF) 34 Page - SMSC Corporation

LAN91C100FD Datasheet(HTML) 34 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Datasheet Download

Link URL