LAN91C100FD datasheet(36/79 Pages) SMSC

36 / 79 page

FEAST Fast Ethernet Controller with Full Duplex Capability

Rev. 10/14/2002

Page 36

SMSC DS – LAN91C100FD Rev. D

PRELIMINARY

Clearing the LE ENABLE bit in the Control Register if an EPH interrupt is caused by a LINK_OK

transition.

Reading the Counter Register if an EPH interrupt is caused by statistics counter roll over.

Setting TXENA bit high if an EPH interrupt is caused by any of the fatal transmit error listed above (3.1

to 3.5).

RX_OVRN INT - Set when 1) the receiver aborts due to an overrun due to a failed memory allocation, 2)

the receiver aborts due to a packet length of greater than 2K bytes, or 3) the receiver aborts due to the

RCV DISCRD bit in the ERCV register set. The RX_OVRN INT bit latches the condition for the purpose of

being polled or generating an interrupt, and will only be cleared by writing the acknowledge register with

the RX_OVRN INT bit set.

ALLOC INT - Set when an MMU request for TX RAM page is successful. This bit is the complement of the

FAILED bit in the ALLOCATION RESULT register. The ALLOC INT bit is cleared by the MMU when the

next allocation request is processed or allocation fails.

TX EMPTY INT - Set if the TX FIFO goes empty, can be used to generate a single interrupt at the end of a

sequence of packets enqueued for transmission. This bit latches the empty condition, and the bit will stay

set until it is specifically cleared by writing the acknowledge register with the TX EMPTY INT bit set. If a

real time reading of the FIFO empty is desired, the bit should be first cleared and then read.

The TX EMPTY Mask bit should only be set after the following steps:

a packet is enqueued for transmission

the previous empty condition is cleared (acknowledged)

TX INT - Set when at least one packet transmission was completed or any of the below transmit fatal

errors occurs:

TXUNRN - Transmit under-run

SQET - SQE Error

LOST CARR - Lost Carrier

LATCOL - Late Collision

16COL - 16 collisions

The first packet number to be serviced can be read from the FIFO PORTS register. The TX INT bit is

always the logic complement of the TEMPTY bit in the FIFO PORTS register. After servicing a packet

number, its TX INT interrupt is removed by writing the Interrupt Acknowledge Register with the TX INT bit

set.

RCV INT - Set when a receive interrupt is generated. The first packet number to be serviced can be read

from the FIFO PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the

FIFO PORTS register. The Receive Interrupt is cleared when RX FIFO is empty.

LAN91C100FD Datasheet(PDF) 36 Page - SMSC Corporation