LAN91C100FD datasheet(3/79 Pages) SMSC

3 / 79 page

FEAST Fast Ethernet Controller with Full Duplex Capability

SMSC DS – LAN91C100FD Rev. D

Page 3

Rev. 10/14/2002

PRELIMINARY

TABLE OF CONTENTS

Chapter 1

General Description .............................................................................................................5

Chapter 2

Pin Configuration................................................................................................................. 6

Chapter 3

Description of Pin Functions ............................................................................................... 7

Chapter 4

Functional Description....................................................................................................... 15

4.1

Description of Block........................................................................................................................... 15

4.1.1

Clock Generator Block............................................................................................................................15

4.2

CSMA/CD BLOCK............................................................................................................................. 15

4.2.1

DMA Block..............................................................................................................................................15

4.2.2

Arbiter Block ...........................................................................................................................................15

4.2.3

MMU Block .............................................................................................................................................16

4.2.4

BIU Block................................................................................................................................................16

4.2.5

MAC-PHY Interface Block ......................................................................................................................16

4.2.6

MII Management Interface Block ............................................................................................................17

4.2.7

Serial EEPROM Interface .......................................................................................................................17

Chapter 5

Data Structures and Registers .......................................................................................... 19

5.1

Packet Format in Buffer Memory ...................................................................................................... 19

5.2

Typical Flow of Events for Transmit (Auto Release = 0)................................................................... 41

5.3

Typical Flow of Events for Transmit (Auto Release = 1)................................................................... 43

5.4

Typical Flow of Events for Receive ................................................................................................... 44

5.5

Memory Partitioning .......................................................................................................................... 49

5.6

Interrupt Generation .......................................................................................................................... 50

Chapter 6

Board Setup Information .................................................................................................. 53

Chapter 7

Application Considerations ............................................................................................... 56

7.1

Fast Ethernet Slave Adapter ............................................................................................................. 56

7.2

VL Local Bus 32 Bit Systems ............................................................................................................ 56

7.3

High End ISA or Non-Burst EISA Machines...................................................................................... 59

7.4

EISA 32 Bit SLAVEEISA 32 Bit Slave............................................................................................... 61

Chapter 8

Operational Description .................................................................................................... 64

8.1

Maximum Guaranteed Ratings* ........................................................................................................ 64

8.2

DC Electrical Characteristics............................................................................................................. 64

Chapter 9

Timing Diagrams................................................................................................................ 67

Chapter 10

Package Outlines............................................................................................................. 77

Chapter 11

LAN91C100FD REV. D Revisions ................................................................................ 79

LIST OF FIGURES

Figure 3.1 - LAN91C100FD Block Diagram .................................................................................................................13

Figure 3.2 - LAN91C100FD System Diagram ..............................................................................................................14

Figure 4.1 - LAN91C100FD Internal Bock diagram with Data Path..............................................................................18

Figure 5.1 - Data Packet Format ..................................................................................................................................19

Figure 5.2 - Interrupt Structure.....................................................................................................................................37

Figure 5.3 - Interrupt Service Routine ..........................................................................................................................45

Figure 5.4 - RX INTR ...................................................................................................................................................46

Figure 5.5 - TX INTR....................................................................................................................................................47

Figure 5.6 - TXEMPTY INTR (Assumes Auto release Option Selected) ......................................................................48

LAN91C100FD Datasheet(PDF) 3 Page - SMSC Corporation

LAN91C100FD Datasheet(HTML) 3 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Datasheet Download

Link URL