LAN91C100FD datasheet(33/79 Pages) SMSC

33 / 79 page

FEAST Fast Ethernet Controller with Full Duplex Capability

SMSC DS – LAN91C100FD Rev. D

Page 33

Rev. 10/14/2002

PRELIMINARY

ALLOCATED PACKET NUMBER - Packet number associated with the last memory allocation request.

The value is only valid if the FAILED bit is clear.

Note:

For software compatibility with future versions, the value read from the ARR after an allocation request is

intended to be written into the PNR as is, without masking higher bits (provided FAILED = 0).

BANK 2

OFFSET

NAME

TYPE

SYMBOL

FIFO PORTS REGISTER

READ ONLY

FIFO

This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO.

The packet numbers to be processed by the interrupt service routines are read from this register.

HIGH

BYTE

REMPTY

RX FIFO PACKET NUMBER

LOW

BYTE

TEMPTY

TX DONE PACKET NUMBER

REMPTY - No receive packets queued in the RX FIFO. For polling purposes, uses the RCV_INT bit in the

Interrupt Status Register.

TOP OF RX FIFO PACKET NUMBER - Packet number presently at the output of the RX FIFO. Only valid

if REMPTY is clear. The packet is removed from the RX FIFO using MMU Commands 3) or 4).

TEMPTY - No transmit packets in completion queue. For polling purposes, uses the TX_INT bit in the

Interrupt Status Register.

TX DONE PACKET NUMBER - Packet number presently at the output of the TX Completion FIFO. Only

valid if TEMPTY is clear. The packet is removed when a TX INT acknowledge is issued.

Note:

For software compatibility with future versions, the value read from each FIFO register is intended to be

written into the PNR as is, without masking higher bits (provided TEMPTY and REMPTY = 0 respectively).

BANK 2

OFFSET

NAME

TYPE

SYMBOL

POINTER REGISTER

READ/WRITE

NOT EMPTY is a read

only bit

PTR

HIGH

BYTE

RCV

AUTO

INCR.

READ

ETEN

NOT

EMPTY

POINTER HIGH

LOW

BYTE

POINTER LOW

POINTER REGISTER - The value of this register determines the address to be accessed within the

transmit or receive areas. It will auto-increment on accesses to the data register when AUTO INCR. is set.

The increment is by one for every byte access, by two for every word access, and by four for every double

word access. When RCV is set the address refers to the receive area and uses the output of RX FIFO as

the packet number, when RCV is clear the address refers to the transmit area and uses the packet number

at the Packet Number Register.

LAN91C100FD Datasheet(PDF) 33 Page - SMSC Corporation

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