UCC28C53_V01 datasheet(34/48 Pages) TI

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9.2.2.10.4 Compensation Loop

The design of the compensation loop involves selecting the appropriate components so that the required gain,

poles, and zeros can be designed to result in a stable system over the entire operating range. There are three

distinct portions of the loop: the TL431, the opto-coupler, and the error amplifier. Each of these stages combines

with the power stage to result in a stable robust system.

For good transient response, the bandwidth of the finalized design must be as large as possible. The bandwidth

of a CCM flyback, fBW, is limited to ¼ of the RHP zero frequency, or approximately 1.77 kHz using Equation 41.

BW =

RHPz

(41)

The gain of the open-loop power stage at fBW can be calculated using Equation 40 or can be observed on the

Bode plot (Figure 9-4) and is equal to –19.55 dB and the phase at fBW is equal to –58°.

The secondary side portion of the compensation loop begins with establishing the regulated steady state output

voltage. To set the regulated output voltage, a TL431 adjustable precision shunt regulator is ideally suited for

use on the secondary side of isolated converters due to its accurate voltage reference and internal op-amp.

The resistors used in the divider from the output terminals of the converter to the TL431 REF pin are selected

based upon the desired power consumption. Because the REF input current for the TL431 is only 2 µA, selecting

the resistors for a divider current (IFB_REF) of 1 mA results in minimal error. The top divider resistor (RFBU) is

calculated:

RFBU =

VOUT F REFTL431

IFB _REF

(42)

The TL431 reference voltage (REFTL431) has a typical value of 2.495 V. A 9.53-kΩ resistor is chosen for RFBU. To

set the output voltage to 12 V, 2.49 kΩ is used for RFBB.

FBB =

REF

TL431

OUT

F REFTL431

× R

FBU

(43)

For good phase margin, a compensator zero (fCOMPz) is required and should be placed at 1/10th the desired

bandwidth:

COMPz

(44)

COMPz

= 2 × N × f

COMPz

(45)

With this converter, fCOMPz should be set at approximately 177 Hz. A series resistor (RCOMPz) and capacitor

(CCOMPz) placed across the TL431 cathode to REF sets the compensator zero location. Setting CCOMPz to

0.01 µF, RCOMPz is calculated:

COMPz

× C

COMPz

(46)

Using a standard value of 88.7 kΩ for RZ and a 0.01 µF for CZ results in a zero placed at 179 Hz.

In Figure 9-3, RTLbias provides cathode current to the TL431 from the regulated voltage provided from the Zener

diode (DREG). For robust performance, 10 mA is provided to bias the TL431 by way of the 10-V Zener and a

1-kΩ resistor is used for RTLbias.

The gain of the TL431 portion of the compensation loop is calculated with Equation 47.

UCC28C53, UCC28C54, UCC28C55

UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59

SLUSER8 – JUNE 2022

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