SH7708 datasheet(138/633 Pages) RENESAS

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6.5

Interrupt Response Time

The time from generation of an interrupt request until interrupt exception handling is performed

and fetching of the first instruction of the exception handler is started (the interrupt response time)

is shown in table 6.6. Figure 6.4 shows an example of pipeline operation when an IRL interrupt is

accepted. When SR.BL is 1, interrupt exception handling is masked, and is kept waiting until

completion of an instruction that clears BL to 0.

Table 6.6

Interrupt Response Time

Number of States

Item

NMI

IRL

Supporting

Modules

Notes

Time for priority

decision and SR mask

bit comparison

0.5

× Icyc

+ 0.5

× Bcyc

+ 0.5

× Pcyc

0.5

× Icyc

+ 0.5

× Bcyc

+ 2

× Pcyc

0.5

× Icyc

+ 1.5

× Pcyc

Wait time until end of

sequence being

executed by CPU

X (

≥ 0) × Icyc

X (

≥ 0) × Icyc

X (

≥ 0) × Icyc

Interrupt exception

handling is kept waiting

until the executing

instruction ends. If the

number of instruction

execution states is S*1,

the maximum wait time

is:

X = S – 1. However, if

BL is set to 1 by

instruction execution or

by an exception,

interrupt exception

handling is deferred

until completion of an

instruction that clears

BL to 0. If the following

instruction masks

interrupt exception

handling, the handling

may be further deferred.

Time from interrupt

exception handling

(save of SR and PC)

until fetch of first

instruction of

exception handler is

started

× Icyc

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