COP8CCR9IMT7SLASHNOPB datasheet(26/111 Pages) TI1

26 / 111 page

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I – OCTOBER 2000 – REVISED MARCH 2013

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NOTE

The actual memory address of the Option Register is 7FFF (hex), however the

MICROWIRE/PLUS ISP routines require the address FFFF (hex) to be used to read the

Option Register when the Flash Memory is secured.

The entire Option Register must be programmed at one time and cannot be rewritten without first erasing

the entire last page of Flash Memory.

5.7

RESET

The device is initialized when the RESET pin is pulled low or the On-chip Brownout Reset is activated.

The Brownout Reset feature is not available on the COP8CDR9.

Figure 5-2. Reset Logic

The following occurs upon initialization:

Port A: TRI-STATE (High Impedance Input)

Port B: TRI-STATE (High Impedance Input)

Port C: TRI-STATE (High Impedance Input)

Port D: HIGH

Port E: TRI-STATE (High Impedance Input)

Port F: TRI-STATE (High Impedance Input)

Port G: TRI-STATE (High Impedance Input). Exceptions: If Watchdog is enabled, then G1 is

Watchdog output. G0 and G2 have their weak pull-up enabled during RESET.

Port L: TRI-STATE (High Impedance Input)

PC: CLEARED to 0000

PSW, CNTRL and ICNTRL registers: CLEARED

SIOR:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

T2CNTRL: CLEARED

T3CNTRL: CLEARED

HSTCR: CLEARED

ITMR: Cleared except Bit 6 (HSON) = 1

Accumulator, Timer 1, Timer 2 and Timer 3:

RANDOM after RESET

WKEN, WKEDG: CLEARED

WKPND: RANDOM

Functional Description

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Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CCR9IMT7/NOPB Datasheet(PDF) 26 Page - Texas Instruments