COP8CCR9IMT7SLASHNOPB datasheet(67/111 Pages) TI1

67 / 111 page

COP8CBR9, COP8CCR9, COP8CDR9

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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013

Where:

BR is the Baud Rate

FC is the crystal frequency

N is the Baud Rate Divisor (Table 5-16)

P is the Prescaler Divide Factor selected by the value in the Prescaler Select Register (Table 5-17)

NOTE

In the Synchronous Mode, the divisor 16 is replaced by two.

Example:

Asynchronous Mode:

Crystal Frequency = 5 MHz

Desired baud rate = 19200

Using the above equation N × P can be calculated first.

N × P = (5 x 10

6 x 2)/(16 x 19200) = 32.552

Now 32.552 is divided by each Prescaler Factor (Table 5-17) to obtain a value closest to an integer. This

factor happens to be 6.5 (P = 6.5).

N = 32.552/6.5 = 5.008 (N = 5)

The programmed value (from Table 5-16) should be 4 (N - 1).

Using the above values calculated for N and P:

BR = (5 x 10

6 x 2)/(16 x 5 x 6.5) = 19230.769

error = (19230.769 - 19200) x 100/19200 = 0.16%

Figure 5-19. USART BAUD Clock Divisor Registers

5.13.8 EFFECT OF HALT/IDLE

The USART logic is reinitialized when either the HALT or IDLE modes are entered. This reinitialization

sets the TBMT flag and resets all read only bits in the USART control and status registers. Read/Write bits

remain unchanged. The Transmit Buffer (TBUF) is not affected, but the Transmit Shift register (TSFT) bits

are set to one. The receiver registers RBUF and RSFT are not affected.

The device will exit from the HALT/IDLE modes when the Start bit of a character is detected at the RDX

(L3) pin. This feature is obtained by using the Multi-Input Wake-up scheme provided on the device.

Before entering the HALT or IDLE modes the user program must select the Wake-up source to be on the

RDX pin. This selection is done by setting bit 3 of WKEN (Wake-up Enable) register. The Wake-up trigger

condition is then selected to be high to low transition. This is done via the WKEDG register (Bit 3 is one).

If the device is halted and crystal oscillator is used, the Wake-up signal will not start the chip running

immediately because of the finite start up time requirement of the crystal oscillator. The idle timer (T0)

generates a fixed (256 tC) delay to ensure that the oscillator has indeed stabilized before allowing the

device to execute code. The user has to consider this delay when data transfer is expected immediately

after exiting the HALT mode.

Functional Description

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COP8CCR9IMT7/NOPB Datasheet(PDF) 67 Page - Texas Instruments

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