COP8CCR9IMT7SLASHNOPB datasheet(76/111 Pages) TI1

76 / 111 page

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I – OCTOBER 2000 – REVISED MARCH 2013

www.ti.com

5.15.3 VIS INSTRUCTION

The general interrupt service routine, which starts at address 00FF Hex, must be capable of handling all

types of interrupts. The VIS instruction, together with an interrupt vector table, directs the device to the

specific interrupt handling routine based on the cause of the interrupt.

VIS is a single-byte instruction, typically used at the very beginning of the general interrupt service routine

at address 00FF Hex, or shortly after that point, just after the code used for context switching. The VIS

instruction determines which enabled and pending interrupt has the highest priority, and causes an indirect

jump to the address corresponding to that interrupt source. The jump addresses (vectors) for all possible

interrupts sources are stored in a vector table.

The vector table may be as long as 32 bytes (maximum of 16 vectors) and resides at the top of the 256-

byte block containing the VIS instruction. However, if the VIS instruction is at the very top of a 256-byte

block (such as at 00FF Hex), the vector table resides at the top of the next 256-byte block. Thus, if the

VIS instruction is located somewhere between 00FF and 01DF Hex (the usual case), the vector table is

located between addresses 01E0 and 01FF Hex. If the VIS instruction is located between 01FF and 02DF

Hex, then the vector table is located between addresses 02E0 and 02FF Hex, and so on.

Each vector is 15 bits long and points to the beginning of a specific interrupt service routine somewhere in

the 32-kbyte memory space. Each vector occupies two bytes of the vector table, with the higher-order byte

at the lower address. The vectors are arranged in order of interrupt priority. The vector of the maskable

interrupt with the lowest rank is located to 0yE0 (higher-order byte) and 0yE1 (lower-order byte). The next

priority interrupt is located at 0yE2 and 0yE3, and so forth in increasing rank. The Software Trap has the

highest rand and its vector is always located at 0yFE and 0yFF. The number of interrupts which can

become active defines the size of the table.

Table 5-27 shows the types of interrupts, the interrupt arbitration ranking, and the locations of the

corresponding vectors in the vector table.

The vector table should be filled by the user with the memory locations of the specific interrupt service

routines. For example, if the Software Trap routine is located at 0310 Hex, then the vector location 0yFE

and -0yFF should contain the data 03 and 10 Hex, respectively. When a Software Trap interrupt occurs

and the VIS instruction is executed, the program jumps to the address specified in the vector table.

The interrupt sources in the vector table are listed in order of rank, from highest to lowest priority. If two or

more enabled and pending interrupts are detected at the same time, the one with the highest priority is

serviced first. Upon return from the interrupt service routine, the next highest-level pending interrupt is

serviced.

If the VIS instruction is executed, but no interrupts are enabled and pending, the lowest-priority interrupt

vector is used, and a jump is made to the corresponding address in the vector table. This is an unusual

occurrence and may be the result of an error. It can legitimately result from a change in the enable bits or

pending flags prior to the execution of the VIS instruction, such as executing a single cycle instruction

which clears an enable flag at the same time that the pending flag is set. It can also result, however, from

inadvertent execution of the VIS command outside of the context of an interrupt.

The default VIS interrupt vector can be useful for applications in which time critical interrupts can occur

during the servicing of another interrupt. Rather than restoring the program context (A, B, X, etc.) and

executing the RETI instruction, an interrupt service routine can be terminated by returning to the VIS

instruction. In this case, interrupts will be serviced in turn until no further interrupts are pending and the

default VIS routine is started. After testing the GIE bit to ensure that execution is not erroneous, the

routine should restore the program context and execute the RETI to return to the interrupted program.

This technique can save up to fifty instruction cycles (tC), or more, (25 µs at 10 MHz oscillator) of latency

for pending interrupts with a penalty of fewer than ten instruction cycles if no further interrupts are

pending.

Functional Description

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CCR9IMT7/NOPB Datasheet(PDF) 76 Page - Texas Instruments

COP8CCR9IMT7/NOPB Datasheet(HTML) 76 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL