COP8CCR9IMT7SLASHNOPB datasheet(75/111 Pages) TI1

75 / 111 page

COP8CBR9, COP8CCR9, COP8CDR9

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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013

Upon Reset, all pending bits, individual enable bits, and the GIE bit are reset to zero. Thus, a maskable

interrupt condition cannot trigger an interrupt until the program enables it by setting both the GIE bit and

the individual enable bit. When enabling an interrupt, the user should consider whether or not a previously

activated (set) pending bit should be acknowledged. If, at the time an interrupt is enabled, any previous

occurrences of the interrupt should be ignored, the associated pending bit must be reset to zero prior to

enabling the interrupt. Otherwise, the interrupt may be simply enabled; if the pending bit is already set, it

will immediately trigger an interrupt. A maskable interrupt is active if its associated enable and pending

bits are set.

An interrupt is an asychronous event which may occur before, during, or after an instruction cycle. Any

interrupt which occurs during the execution of an instruction is not acknowledged until the start of the next

normally executed instruction. If the next normally executed instruction is to be skipped, the skip is

performed before the pending interrupt is acknowledged.

At the start of interrupt acknowledgment, the following actions occur:

1. The GIE bit is automatically reset to zero, preventing any subsequent maskable interrupt from

interrupting the current service routine. This feature prevents one maskable interrupt from interrupting

another one being serviced.

2. The address of the instruction about to be executed is pushed onto the stack.

3. The program counter (PC) is loaded with 00FF Hex, causing a jump to that program memory location.

The device requires seven instruction cycles to perform the actions listed above.

If the user wishes to allow nested interrupts, the interrupts service routine may set the GIE bit to 1 by

writing to the PSW register, and thus allow other maskable interrupts to interrupt the current service

routine. If nested interrupts are allowed, caution must be exercised. The user must write the program in

such a way as to prevent stack overflow, loss of saved context information, and other unwanted

conditions.

The interrupt service routine stored at location 00FF Hex should use the VIS instruction to determine the

cause of the interrupt, and jump to the interrupt handling routine corresponding to the highest priority

enabled and active interrupt. Alternately, the user may choose to poll all interrupt pending and enable bits

to determine the source(s) of the interrupt. If more than one interrupt is active, the user's program must

decide which interrupt to service.

Within a specific interrupt service routine, the associated pending bit should be cleared. This is typically

done as early as possible in the service routine in order to avoid missing the next occurrence of the same

type of interrupt event. Thus, if the same event occurs a second time, even while the first occurrence is

still being serviced, the second occurrence will be serviced immediately upon return from the current

interrupt routine.

An interrupt service routine typically ends with an RETI instruction. This instruction set the GIE bit back to

1, pops the address stored on the stack, and restores that address to the program counter. Program

execution then proceeds with the next instruction that would have been executed had there been no

interrupt. If there are any valid interrupts pending, the highest-priority interrupt is serviced immediately

upon return from the previous interrupt.

NOTE

While executing from the Boot ROM for ISP or virtual E2 operations, the hardware will

disable interrupts from occurring. The hardware will leave the GIE bit in its current state, and

if set, the hardware interrupts will occur when execution is returned to Flash Memory.

Subsequent interrupts, during ISP operation, from the same interrupt source will be lost.

Functional Description

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Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CCR9IMT7/NOPB Datasheet(PDF) 75 Page - Texas Instruments

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