COP8CCR9IMT7SLASHNOPB datasheet(57/111 Pages) TI1

57 / 111 page

COP8CBR9, COP8CCR9, COP8CDR9

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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013

The IDLE mode uses the on-chip IDLE Timer (Timer T0) to keep track of elapsed time in the IDLE state.

The IDLE Timer runs continuously at the low speed clock rate, whether or not the device is in the IDLE

mode. Each time the bit of the timer associated with the selected window toggles, the T0PND bit is set, an

interrupt is generated (if enabled), and the device exits the IDLE mode if in that mode. If the IDLE Timer

interrupt is enabled, the interrupt is serviced before execution of the main program resumes. (However,

the instruction which was started as the part entered the IDLE mode is completed before the interrupt is

serviced. This instruction should be a NOP which should follow the enter IDLE instruction.) The user must

reset the IDLE Timer pending flag (T0PND) before entering the IDLE mode.

As with the HALT mode, this device can also be returned to normal operation with a Multi-Input Wake-up

input.

The IDLE Timer cannot be started or stopped under software control, and it is not memory mapped, so it

cannot be read or written by the software. Its state upon Reset is unknown. Therefore, if the device is put

into the IDLE mode at an arbitrary time, it will stay in the IDLE mode for somewhere between 30 µs and

the selected time period.

In order to precisely time the duration of the IDLE state, entry into the IDLE mode must be synchronized to

the state of the IDLE Timer. The best way to do this is to use the IDLE Timer interrupt, which occurs on

every underflow of the bit of the IDLE Timer which is associated with the selected window. Another

method is to poll the state of the IDLE Timer pending bit T0PND, which is set on the same occurrence.

The Idle Timer interrupt is enabled by setting bit T0EN in the ICNTRL register.

Any time the IDLE Timer window length is changed there is the possibility of generating a spurious IDLE

Timer interrupt by setting the T0PND bit. The user is advised to disable IDLE Timer interrupts prior to

changing the value of the ITSEL bits of the ITMR Register and then clear the T0PND bit before attempting

to synchronize operation to the IDLE Timer.

As with the HALT mode, it is necessary to program two NOP's to allow clock resynchronization upon

return from the IDLE mode. The NOP's are placed either at the beginning of the IDLE Timer interrupt

routine or immediately following the “enter IDLE mode” instruction.

For more information on the IDLE Timer and its associated interrupt, see the description in the Timer T0

(IDLE Timer).

Figure 5-15. Multi-Input Wake-Up Logic

Functional Description

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COP8CCR9IMT7/NOPB Datasheet(PDF) 57 Page - Texas Instruments