COP8CCR9IMT7SLASHNOPB datasheet(61/111 Pages) TI1

61 / 111 page

COP8CBR9, COP8CCR9, COP8CDR9

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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013

PE = 0

Indicates no Parity Error has been detected since the last time the ENUR register was read.

PE = 1

Indicates the occurrence of a Parity Error.

BD: Flags a line break.

BD = 0

Indicates no Line Break has been detected since the last time the ENUR register was read.

BD = 1

Indicates the occurrence of a Line Break.

RBIT9: Contains the ninth data bit received when the USART is operating with nine data bits per frame.

Read only, cleared on reset.

ATTN: ATTENTION Mode is enabled while this bit is set. This bit is cleared automatically on receiving a

character with data bit nine set. Read/Write, cleared on reset.

XMTG: This bit is set to indicate that the USART is transmitting. It gets reset at the end of the last frame

(end of last Stop bit). Read only, cleared on reset.

RCVG: This bit is set high whenever a framing error or a break detect occurs and goes low when RDX

goes high. Read only, cleared on reset.

ENUI—USART INTERRUPT AND CLOCK SOURCE REGISTER (Address at 0BC)

STP2

BRK

ETDX

SSEL

XRCLK

XTCLK

ERI

ETI

Bit 7

Bit 0

STP2: This bit programs the number of Stop bits to be transmitted. Read/Write, cleared on reset.

STP2 = 0

One Stop bit transmitted.

STP2 = 1

Two Stop bits transmitted.

BRK: Holds TDX (USART Transmit Pin) low to generate a Line Break. Timing of the Line Break is under

software control.

ETDX: TDX (USART Transmit Pin) is the alternate function assigned to Port L pin L2; it is selected by

setting ETDX bit.

SSEL: USART mode select. Read only, cleared on reset.

SSEL = 0

Asynchronous Mode.

SSEL = 1

Synchronous Mode.

XRCLK: This bit selects the clock source for the receiver section. Read/Write, cleared on reset.

XRCLK = 0

The clock source is selected through the PSR and BAUD registers.

XRCLK = 1

Signal on CKX (L1) pin is used as the clock.

XTCLK: This bit selects the clock source for the transmitter section. Read/Write, cleared on reset.

XTCLK = 0

The clock source is selected through the PSR and BAUD registers.

XTCLK = 1

Signal on CKX (L1) pin is used as the clock.

ERI: This bit enables/disables interrupt from the receiver section. Read/Write, cleared on reset.

ERI = 0

Interrupt from the receiver is disabled.

ERI = 1

Interrupt from the receiver is enabled.

ETI: This bit enables/disables interrupt from the transmitter section. Read/Write, cleared on reset.

ETI = 0

Interrupt from the transmitter is disabled.

ETI = 1

Interrupt from the transmitter is enabled.

Functional Description

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Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CCR9IMT7/NOPB Datasheet(PDF) 61 Page - Texas Instruments

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