COP8CCR9IMT7SLASHNOPB datasheet(44/111 Pages) TI1

44 / 111 page

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I – OCTOBER 2000 – REVISED MARCH 2013

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Any time the IDLE Timer period is changed there is the possibility of generating a spurious IDLE Timer

interrupt by setting the T0PND bit. The user is advised to disable IDLE Timer interrupts prior to changing

the value of the ITSEL bits of the ITMR Register and then clear the T0PND bit before attempting to

synchronize operation to the IDLE Timer.

5.11.2 TIMER T1, TIMER T2, AND TIMER T3

The device has a set of three powerful timer/counter blocks, T1, T2, and T3. Since T1, T2 and T3 are

identical, except for the high speed operation of T2 and T3, all comments are equally applicable to any of

the three timer blocks which will be referred to as Tx. Differences between the timers will be specifically

noted.

Each timer block consists of a 16-bit timer, Tx, and two supporting 16-bit autoreload/capture registers,

RxA and RxB. Each timer block has two pins associated with it, TxA and TxB. The pin TxA supports I/O

required by the timer block, while the pin TxB is an input to the timer block. The timer block has three

operating modes: Processor Independent PWM mode, External Event Counter mode, and Input Capture

mode.

The control bits TxC3, TxC2, and TxC1 allow selection of the different modes of operation.

5.11.2.1 Timer Operating Speeds

Each of the Tx timers, except T1, have the ability to operate at either the instruction cycle frequency (low

speed) or the internal clock frequency (MCLK). For 10 MHz CKI, the instruction cycle frequency is 2 MHz

and the internal clock frequency is 20 MHz. This feature is controlled by the High Speed Timer Control

appropriate TxHS bit to 1. For low speed operation, clear the appropriate TxHS bit to 0. This register is

cleared to 00 on Reset.

HSTCR

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

T3HS

T2HS

5.11.2.2 Mode 1. Processor Independent PWM Mode

One of the timer's operating modes is the Processor Independent PWM mode. In this mode, the timers

generate a “Processor Independent” PWM signal because once the timer is set up, no more action is

required from the CPU which translates to less software overhead and greater throughput. The user

software services the timer block only when the PWM parameters require updating. This capability is

provided by the fact that the timer has two separate 16-bit reload registers. One of the reload registers

contains the “ON” time while the other holds the “OFF” time. By contrast, a microcontroller that has only a

single reload register requires an additional software to update the reload value (alternate between the on-

time/off-time).

The timer can generate the PWM output with the width and duty cycle controlled by the values stored in

the reload registers. The reload registers control the countdown values and the reload values are

automatically written into the timer when it counts down through 0, generating interrupt on each reload.

Under software control and with minimal overhead, the PWM outputs are useful in controlling motors,

triacs, the intensity of displays, and in providing inputs for data acquisition and sine wave generators.

In this mode, the timer Tx counts down at a fixed rate of tC (T2 and T3 may be selected to operate from

MCLK). Upon every underflow the timer is alternately reloaded with the contents of supporting registers,

RxA and RxB. The very first underflow of the timer causes the timer to reload from the register RxA.

Subsequent underflows cause the timer to be reloaded from the registers alternately beginning with the

Figure 5-10 shows a block diagram of the timer in PWM mode.

Functional Description

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