COP8CCR9IMT7SLASHNOPB datasheet(74/111 Pages) TI1

74 / 111 page

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I – OCTOBER 2000 – REVISED MARCH 2013

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Figure 5-23 shows the Interrupt block diagram.

Figure 5-23. Interrupt Block Diagram

5.15.2 MASKABLE INTERRUPTS

All interrupts other than the Software Trap are maskable. Each maskable interrupt has an associated

enable bit and pending flag bit. The pending bit is set to 1 when the interrupt condition occurs. The state

of the interrupt enable bit, combined with the GIE bit determines whether an active pending flag actually

triggers an interrupt. All of the maskable interrupt pending and enable bits are contained in mapped

control registers, and thus can be controlled by the software.

A maskable interrupt condition triggers an interrupt under the following conditions:

1. The enable bit associated with that interrupt is set.

2. The GIE bit is set.

3. The device is not processing a non-maskable interrupt. (If a non-maskable interrupt is being serviced,

a maskable interrupt must wait until that service routine is completed.)

An interrupt is triggered only when all of these conditions are met at the beginning of an instruction. If

different maskable interrupts meet these conditions simultaneously, the highest-priority interrupt will be

serviced first, and the other pending interrupts must wait.

Functional Description

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