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COP8CCR9IMT7/NOPB Datasheet(PDF) 12 Page - Texas Instruments |
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COP8CCR9IMT7/NOPB Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 111 page  COP8CBR9, COP8CCR9, COP8CDR9 SNOS535I – OCTOBER 2000 – REVISED MARCH 2013 www.ti.com Electrical Characteristics DC Electrical Characteristics ( −40°C ≤ TA ≤ +85°C) (continued) Datasheet min/max specification limits are ensured by design, test, or statistical analysis. Parameter Conditions Min Typ Max Units Supply Current for BOR Feature VCC = 5.5V 45 μA 4.28 High Brownout Trip Level (BOR Enabled) 4.17 4.5 V Low Brownout Trip Level (BOR Enabled) 2.7 2.78 2.9 V Input Levels (VIH, VIL) Logic High 0.8 VCC V Logic Low 0.16 VCC V Internal Bias Resistor for the CKI 0.3 1.0 2.5 M Ω Crystal/Resonator Oscillator Hi-Z Input Leakage VCC = 5.5V −0.5 +0.5 μA Input Pullup Current VCC = 5.5V, VIN = 0V −50 −210 μA Port Input Hysteresis 0.25 VCC V Output Current Levels D Outputs Source VCC = 4.5V, VOH = 3.8V −7 mA VCC = 2.7V, VOH = 1.8V −4 mA Sink(4) VCC = 4.5V, VOL = 1.0V 10 mA VCC = 2.7V, VOL = 0.4V 3.5 mA All Others Source (Weak Pull-Up Mode) VCC = 4.5V, VOH = 3.8V −10 μA VCC = 2.7V, VOH = 1.8V −5 μA Source (Push-Pull Mode) VCC = 4.5V, VOH = 3.8V −7 mA VCC = 2.7V, VOH = 1.8V −4 mA Sink (Push-Pull Mode)(4) VCC = 4.5V, VOL = 1.0V 10 mA VCC = 2.7V, VOL = 0.4V 3.5 mA TRI-STATE Leakage VCC = 5.5V −0.5 +0.5 μA Allowable Sink Current per Pin 15 mA Maximum Input Current without Latchup(5) ±200 mA RAM Retention Voltage, VR (in HALT Mode) 2.0 V Input Capacitance 7 pF Load Capacitance on D2 1000 pF Voltage on G6 to Force Execution from Boot ROM(6) G6 rise time must be slower than 2 x VCC VCC + 7 V 100 ns G6 Rise Time to Force Execution from Boot ROM 100 nS Input Current on G6 when Input > VCC VIN = 11V, VCC = 5.5V 500 μA Flash Memory Data Retention 25°C 100 yrs Flash Memory Number of Erase/Write Cycles SeeTable 5-12, Typical Flash 105 cycles Memory Endurance (4) Absolute Maximum Ratings should not be exceeded. (5) Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). These two pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients. (6) Vcc must be valid and stable before G6 is raised to a high voltage. 12 Electrical Specifications Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9 |
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