COP8CCR9IMT7SLASHNOPB datasheet(55/111 Pages) TI1

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COP8CBR9, COP8CCR9, COP8CDR9

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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013

The IDLE Timer cannot be started or stopped under software control, and it is not memory mapped, so it

cannot be read or written by the software. Its state upon Reset is unknown. Therefore, if the device is put

into the IDLE mode at an arbitrary time, it will stay in the IDLE mode for somewhere between 30 µs and

the selected time period.

In order to precisely time the duration of the IDLE state, entry into the IDLE mode must be ”synchronized

to the state of the IDLE Timer. The best way to do this is to use the IDLE Timer interrupt, which occurs on

every underflow of the bit of the IDLE Timer which is associated with the selected window. Another

method is to poll the state of the IDLE Timer pending bit T0PND, which is set on the same occurrence.

The Idle Timer interrupt is enabled by setting bit T0EN in the ICNTRL register.

Any time the IDLE Timer window length is changed there is the possibility of generating a spurious IDLE

Timer interrupt by setting the T0PND bit. The user is advised to disable IDLE Timer interrupts prior to

changing the value of the ITSEL bits of the ITMR Register and then clear the T0PND bit before attempting

to synchronize operation to the IDLE Timer.

NOTE

As with the HALT mode, it is necessary to program two NOP's to allow clock

resynchronization upon return from the IDLE mode. The NOP's are placed either at the

beginning of the IDLE Timer interrupt routine or immediately following the “enter IDLE mode”

instruction.

For more information on the IDLE Timer and its associated interrupt, see the description in the Timers

section.

5.12.5 LOW SPEED MODE OPERATION

This mode of operation allows for low speed operation of the core clock and low speed operation of the

Idle Timer. Because the low speed oscillator draws very little operating current, and also to expedite

restarting from HALT mode, the low speed oscillator is left on at all times in this mode, including HALT

mode. This is the lowest power mode of operation on the device. This mode can only be entered from the

Dual Clock mode.

To enter the Low Speed mode, the following sequence must be followed using two separate instructions:

1. Software sets the CCKSEL bit to 1.

2. Software clears the HSON bit to 0.

Since the low speed oscillator is already running, there is no clock startup delay.

5.12.5.1 Low Speed HALT Mode

The fully static architecture of this device allows the state of the microcontroller to be frozen. Because the

low speed oscillator draws very minimal operating current, it will be left running in the low speed halt

mode. However, the Idle Timer will not be running. This also allows for a faster exit from HALT. The

processor can be forced to exit the HALT mode and resume normal operation at any time.

During normal operation, the actual power consumption depends heavily on the clock speed and operating

voltage used in an application and is shown in the Electrical Specifications. In the HALT mode, the device

only draws a small leakage current, plus current for the BOR feature (if enabled), plus the 32 kHz

oscillator current, plus any current necessary for driving the outputs. Since total power consumption is

affected by the amount of current required to drive the outputs, all I/Os should be configured to draw

minimal current prior to entering the HALT mode, if possible.

Functional Description

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