COP8CCR9IMT7SLASHNOPB datasheet(29/111 Pages) TI1

29 / 111 page

COP8CBR9, COP8CCR9, COP8CDR9

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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013

Case 2 shows a subsequent dip in the supply voltage which goes below the approximate 1.8V level. As

VCC drops below Vbor, the internal RESET signal is asserted. When VCC rises back above the 1.8V level, td

is started. Since the power supply rise time is longer for this case, td has expired before VCC rises above

Vbor and tid starts immediately when VCC is greater than Vbor.

Case 3 shows a dip in the supply where VCC drops below Vbor, but not below 1.8V. On-chip RESET is

asserted when VCC goes below Vbor and tid starts as soon as the supply goes back above Vbor.

If the Brownout Reset feature is enabled, the internal reset will not be turned off until the Idle Timer

underflows. The internal reset will perform the same functions as external reset. The device is ensured to

operate at the specified frequency down to the specified brownout voltage. After the underflow, the logic is

designed such that no additional internal resets occur as long as VCC remains above the brownout

voltage.

The device is relatively immune to short duration negative-going VCC transients (glitches). It is essential

that good filtering of VCC be done to ensure that the brownout feature works correctly. Power supply

decoupling is vital even in battery powered systems.

There are two optional brownout voltages. The part numbers for the three versions of this device are:

COP8CBR, Vbor = low voltage range

COP8CCR, Vbor = high voltage range

COP8CDR, BOR is disabled.

Refer to the device specifications for the actual Vbor voltages.

High brownout voltage devices are ensured to operate at 10MHz down to the brownout voltage. Low

brownout voltage devices are ensured to operate at 3.33MHz down to the brownout voltage. Devices are

not ensured to operate at 10MHz down to the low brownout voltage.

Under no circumstances should the RESET pin be allowed to float. If the on-chip Brownout Reset feature

is being used, the RESET pin should be connected directly to VCC. The RESET input may also be

connected to an external pull-up resistor or to other external circuitry. Any rising edge on the RESET pin

while VCC is below the specified operating range may cause unpredictable results. The output of the

brownout reset detector will always preset the Idle Timer to a value between 00F0 and 00FF (240 to 256

tC). At this time, the internal reset will be generated.

If the BOR feature is disabled, then no internal resets are generated and the Idle Timer will power-up with

an unknown value. In this case, the external RESET must be used. When BOR is disabled, this on-chip

circuitry is disabled and draws no DC current.

The contents of data registers and RAM are unknown following the on-chip reset.

Figure 5-5. Reset Circuit Using Power-On Reset

5.8

OSCILLATOR CIRCUITS

The device has two crystal oscillators to facilitate low power operation while maintaining throughput when

required. Further information on the use of the two oscillators is found in Power Saving Features. The low

speed oscillator utilizes the L0 and L1 port pins. References in the following text to CKI will also apply to

L0 and references to G7/CKO will also apply to L1.

Functional Description

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Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CCR9IMT7/NOPB Datasheet(PDF) 29 Page - Texas Instruments

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