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EM342-RTR Datasheet(PDF) 56 Page - Silicon Laboratories

Part # EM342-RTR
Description  High-Performance, Integrated RF4CE System-on-Chip
PDF  143 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

EM342-RTR Datasheet(HTML) 56 Page - Silicon Laboratories

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EM342
56
Rev 1.0
GPIO_PACFGH: Address: 0x4000B004 Reset: 0x4444
GPIO_PBCFGH: Address: 0x4000B404 Reset: 0x4444
GPIO_PCCFGH: Address: 0x4000B804 Reset: 0x4444
Register 7.2. GPIO_PxCFGH
GPIO_PACFGH: Port A Configuration Register (High)
GPIO_PBCFGH: Port B Configuration Register (High)
GPIO_PCCFGH: Port C Configuration Register (High)
Bit
31
30
29
28
27
26
25
24
Name
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Name
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
Px7_CFG
Px6_CFG
Bit
7
6
5
4
3
2
1
0
Name
Px5_CFG
Px4_CFG
Bitname
Bitfield Access
Description
Px7_CFG
[15:12]
RW
GPIO configuration control.
0x0: Analog, input or output (GPIO_PxIN always reads 1).
0x1: Output, push-pull (GPIO_PxOUT controls the output).
0x4: Input, floating.
0x5: Output, open-drain (GPIO_PxOUT controls the output).
0x8: Input, pulled up or down (selected by GPIO_PxOUT: 0 = pull-down,
1 = pull-up).
0x9: Alternate output, push-pull (peripheral controls the output).
0xD: Alternate output, open-drain (peripheral controls the output).
Px6_CFG
[11:8]
RW
GPIO configuration control: see Px7_CFG above.
Px5_CFG
[7:4]
RW
GPIO configuration control: see Px7_CFG above.
Px4_CFG
[3:0]
RW
GPIO configuration control: see Px7_CFG above.



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