EM342-RTR datasheet(36/143 Pages) SILABS

36 / 143 page

EM342

Rev 1.0

6.2.1.2. nRESET Pin

A single active low pin, nRESET, is provided to reset the system. This pin has a Schmitt triggered input.

To afford good noise immunity and resistance to switch bounce, the pin is filtered with the Reset Filter module and

generates the pin reset source, nRESET, to the Reset Generation module. Table 6.4 contains the specification for

the filter.

6.2.1.3. Watchdog Reset

The EM342 contains a watchdog timer (see also "6.4.1. Watchdog Timer" on page 43) that is clocked by the

internal 1 kHz timing reference. When the timer expires it generates the reset source WATCHDOG_RESET to the

Reset Generation module.

6.2.1.4. Software Reset

The ARM® CortexTM-M3 CPU can initiate a reset under software control. This is indicated with the reset source

SYSRESETREQ to the Reset Generation module.

6.2.1.5. Option Byte Error

The flash memory controller contains a state machine that reads configuration information from the information

blocks in the flash at system start time. An error check is performed on the option bytes that are read from flash

and, if the check fails, an error is signaled that provides the reset source OPT_BYTE_ERROR to the Reset

Generation module.

If an option byte error is detected, the system restarts and the read and check process is repeated. If the error is

detected again the process is repeated but stops on the 3rd failure. The system is then placed into an emulated

deep sleep where recovery is possible. In this state, flash memory readout protection is forced active to prevent

secure applications from being compromised.

6.2.1.6. Debug Reset

The Serial Wire/JTAG Interface (SWJ) provides access to the SWJ Debug Port (SWJ-DP) registers. By setting the

module.

6.2.1.7. JRST

One of the EM342’s pins can function as the JTAG reset, conforming to the requirements of the JTAG standard.

This input acts independently of all other reset sources and, when asserted, does not reset any on-chip hardware

except for the JTAG TAP. If the EM342 is in the Serial Wire mode or if the SWJ is disabled, this input has no effect.

Table 6.4. Reset Filter Specification for nRESET

Parameter

Min

Typ

Max

Unit

Reset filter time constant

2.1

12.0

16.0

µs

Reset pulse width to guarantee a reset

26.0

—

µs

Reset pulse width guaranteed not to cause a reset

—

1.0

µs

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