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EM342-RTR Datasheet(PDF) 65 Page - Silicon Laboratories

Part # EM342-RTR
Description  High-Performance, Integrated RF4CE System-on-Chip
PDF  143 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

EM342-RTR Datasheet(HTML) 65 Page - Silicon Laboratories

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EM342
Rev 1.0
65
Address: 0x4000A814 Reset: 0x0
Address: 0x4000BC00 Reset: 0x10
Register 7.11. INT_GPIOFLAG: GPIO Interrupt Flag Register
Bit
31
30
29
28
27
26
25
24
Name
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Name
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Name
0
0
0
0
INT_IRQDFLAG INT_IRQCFLAG
0
INT_IRQAFLAG
Bitname
Bitfield Access
Description
INT_IRQDFLAG
[3]
RW
IRQD interrupt pending. Write 1 to clear IRQD interrupt (writing 0 has no effect).
INT_IRQCFLAG
[2]
RW
IRQC interrupt pending. Write 1 to clear IRQC interrupt (writing 0 has no effect).
INT_IRQAFLAG
[0]
RW
IRQA interrupt pending. Write 1 to clear IRQA interrupt (writing 0 has no effect).
Register 7.12. GPIO_DBGCFG: GPIO Debug Configuration Register
Bit
31
30
29
28
27
26
25
24
Name
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Name
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Name
0
0
GPIO_DEBUGDIS
GPIO_EXTREGEN
GPIO_DBGCFGRSVD
0
0
0
Bitname
Bitfield
Access
Description
GPIO_DEBUGDIS
[5]
RW
Disable debug interface override of normal GPIO configuration.
0: Permit debug interface to be active.
1: Disable debug interface (if it is not already active).
GPIO_EXTREGEN
[4]
RW
Enable REG_EN override of PA7's normal GPIO configuration.
0: Disable override.
1: Enable override.
GPIO_DBGCFGRSVD
[3]
RW
Reserved: this bit can change during normal operation. When writing to GPI-
O_DBGCFG, the value of this bit must be preserved.



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