EM342-RTR datasheet(82/143 Pages) SILABS

82 / 143 page

EM342

Rev 1.0

8.4.5. DMA

"8.5. DMA Channels" on page 86 describes how to configure and use the serial receive and transmit DMA

channels.

The receive DMA channel has special provisions to record UART receive errors. When the DMA channel transfers

a character from the receive FIFO to a buffer in memory, it checks the stored parity and frame error status flags.

When an error is flagged, the SC1_RXERRA/B register is updated, marking the offset to the first received

character with a parity or frame error. Similarly if a receive overrun error occurs, the SC1_RXERRA/B registers

mark the error offset. The receive FIFO hardware generates the INT_SCRXOVF interrupt and DMA status register

indicates the error immediately, but in this case the error offset is 4 characters ahead of the actual overflow at the

input to the receive FIFO. Two conditions will clear the error indication: setting the appropriate SC_RXDMARST bit

in the SC1_DMACTRL register, or loading the appropriate DMA buffer after it has unloaded.

8.4.6. Interrupts

UART interrupts are generated on the following events:



Transmit FIFO empty and last character shifted out (depending on SCx_INTMODE, either the 0 to 1

transition or the high level of SC_UARTTXIDLE)



Transmit FIFO changed from full to not full (depending on SCx_INTMODE, either the 0 to 1 transition or the

high level of SC_UARTTXFREE)



Receive FIFO changed from empty to not empty (depending on SCx_INTMODE, either the 0 to 1 transition

or the high level of SC_UARTRXVAL)



Transmit DMA buffer A/B complete (1 to 0 transition of SC_TXACTA/B)



Receive DMA buffer A/B complete (1 to 0 transition of SC_RXACTA/B)



Character received with parity error



Character received with frame error



Character received and lost when receive FIFO was full (receive overrun error)

To enable CPU interrupts, set the desired interrupt bits in the second-level INT_SCxCFG register, and enable the

top-level SCx interrupt in the NVIC by writing the INT_SCx bit in the INT_CFGSET register.

Table 8.6. UART RTS/CTS Flow Control Configurations

SC1_UARTCFG

Pins Used

Operating Mode

SC_UARTxxx*

FLOW AUTO RTS

—

TXD, RXD

No RTS/CTS flow control

0/1

TXD, RXD,

nCTS, nRTS

Flow control using RTS/CTS with software control of nRTS:



nRTS controlled by SC_UARTRTS bit in SC1_UARTCFG register

—

TXD, RXD,

nCTS, nRTS

Flow control using RTS/CTS with hardware control of nRTS:



nRTS is asserted if room for at least 2 characters in receive FIFO

*Note: The notation “xxx” means that the corresponding column header below is inserted to form the field name.

EM342-RTR Datasheet(PDF) 82 Page - Silicon Laboratories

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