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EM342-RTR Datasheet(PDF) 95 Page - Silicon Laboratories |
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EM342-RTR Datasheet(HTML) 95 Page - Silicon Laboratories |
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95 / 143 page ![]() EM342 Rev 1.0 95 SC1_RXCNTA: Address: 0x4000C820 Reset: 0x0 Register 8.24. SC1_RXCNTA: Receive DMA Count Register A Bit 31 30 29 28 27 26 25 24 Name 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Name 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 0 0 SC_RXCNTA Bit 7 6 5 4 3 2 1 0 Name SC_RXCNTA Bitname Bitfield Access Description SC_RXCNTA [13:0] RW The offset from the start of DMA receive buffer A at which the next byte will be written. This register is set to zero when the buffer is loaded and when the DMA is reset. If this register is written when the buffer is not loaded, the buffer is loaded. |
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