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EM342-RTR Datasheet(PDF) 84 Page - Silicon Laboratories |
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EM342-RTR Datasheet(HTML) 84 Page - Silicon Laboratories |
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84 / 143 page ![]() EM342 84 Rev 1.0 SC1_UARTCFG: Address: 0x4000C85C Reset: 0x0 Register 8.10. SC1_UARTCFG: UART Configuration Register Bit 31 30 29 28 27 26 25 24 Name 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Name 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name 0 SC_ UARTAUTO SC_ UARTFLOW SC_ UARTODD SC_ UARTPAR SC_ UART2STP SC_ UART8BIT SC_ UARTRTS Bitname Bitfield Access Description SC_UARTAUTO [6] RW Set this bit to enable automatic nRTS control by hardware (SC_UARTFLOW must also be set). When automatic control is enabled, nRTS will be deasserted when the receive FIFO has space for only one more byte (inhibits transmission from the other device) and will be asserted if it has space for more than one byte (enables trans- mission from the other device). The SC_UARTRTS bit in this register has no effect if this bit is set. SC_UARTFLOW [5] RW Set this bit to enable using nRTS/nCTS flow control signals. Clear this bit to disable the signals. When this bit is clear, the UART transmitter will not be inhibited by nCTS. SC_UARTODD [4] RW If parity is enabled, specifies the kind of parity. 0: Even parity. 1: Odd parity. SC_UARTPAR [3] RW Specifies whether to use parity bits. 0: Don't use parity. 1: Use parity. SC_UART2STP [2] RW Number of stop bits transmitted. 0: 1 stop bit. 1: 2 stop bits. SC_UART8BIT [1] RW Number of data bits. 0: 7 data bits. 1: 8 data bits. SC_UARTRTS [0] RW nRTS is an output to control the flow of serial data sent to the EM342 from another device. This bit directly controls the output at the nRTS pin (SC_UARTFLOW must be set and SC_UARTAUTO must be cleared). When this bit is set, nRTS is asserted (pin is low, 'XON', RS232 positive voltage); the other device's transmission is enabled. When this bit is cleared, nRTS is deasserted (pin is high, 'XOFF', RS232 negative voltage), the other device's transmission is inhibited. |
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