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EM342-RTR Datasheet(PDF) 60 Page - Silicon Laboratories

Part # EM342-RTR
Description  High-Performance, Integrated RF4CE System-on-Chip
PDF  143 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

EM342-RTR Datasheet(HTML) 60 Page - Silicon Laboratories

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EM342
60
Rev 1.0
GPIO_PASET: Address: 0x4000B010 Reset: 0x0
GPIO_PBSET: Address: 0x4000B410 Reset: 0x0
GPIO_PCSET: Address: 0x4000B810 Reset: 0x0
Register 7.6. GPIO_PxSET
GPIO_PASET: Port A Output Set Register
GPIO_PBSET: Port B Output Set Register
GPIO_PCSET: Port C Output Set Register
Bit
31
30
29
28
27
26
25
24
Name
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Name
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
GPIO_PXSETRSVD
Bit
7
6
5
4
3
2
1
0
Name
Px7
Px6
Px5
Px4
Px3
Px2
Px1
Px0
Bitname
Bitfield Access
Description
GPIO_PXSETRSVD
[15:8]
W
Reserved: these bits must be set to 0.
Px7
[7]
W
Write 1 to set the output data bit for Px7 (writing 0 has no effect).
Px6
[6]
W
Write 1 to set the output data bit for Px6 (writing 0 has no effect).
Px5
[5]
W
Write 1 to set the output data bit for Px5 (writing 0 has no effect).
Px4
[4]
W
Write 1 to set the output data bit for Px4 (writing 0 has no effect).
Px3
[3]
W
Write 1 to set the output data bit for Px3 (writing 0 has no effect).
Px2
[2]
W
Write 1 to set the output data bit for Px2 (writing 0 has no effect).
Px1
[1]
W
Write 1 to set the output data bit for Px1 (writing 0 has no effect).
Px0
[0]
W
Write 1 to set the output data bit for Px0 (writing 0 has no effect).



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