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EM342-RTR Datasheet(PDF) 98 Page - Silicon Laboratories

Part # EM342-RTR
Description  High-Performance, Integrated RF4CE System-on-Chip
PDF  143 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

EM342-RTR Datasheet(HTML) 98 Page - Silicon Laboratories

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EM342
98
Rev 1.0
SC1_RXERRA: DMA First Receive Error Register A
Register 8.27. SC1_RXERRA: DMA First Receive Error Register A
Bit
31
30
29
28
27
26
25
24
Name
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Name
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
0
0
SC_RXERRA
Bit
7
6
5
4
3
2
1
0
Name
SC_RXERRA
Bitname
Bitfield Access
Description
SC_RXERRA
[13:0]
R
The offset from the start of DMA receive buffer A of the first byte received
with a parity, frame, or overflow error. Note that an overflow error occurs at
the input to the receive FIFO, so this offset is 4 bytes before the overflow
position. If there is no error, it reads zero. This register will not be updated
by subsequent errors until the buffer unloads and is reloaded, or the
receive DMA is reset.



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