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EM342-RTR Datasheet(PDF) 62 Page - Silicon Laboratories |
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EM342-RTR Datasheet(HTML) 62 Page - Silicon Laboratories |
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62 / 143 page ![]() EM342 62 Rev 1.0 Address: 0x4000BC1C Reset: 0x0 Register 7.8. GPIO_WAKEFILT: GPIO Wakeup Filtering Register Bit 31 30 29 28 27 26 25 24 Name 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Name 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name 0 0 0 0 IRQD_WAKE_ FILTER 0 SC1_WAKE_ FILTER GPIO_WAKE_ FILTER Bitname Bitfield Access Description IRQD_WAKE_FILTER [3] RW Enable filter on GPIO wakeup source IRQD. SC1_WAKE_FILTER [1] RW Enable filter on GPIO wakeup source SC1 (PB2). GPIO_WAKE_FILTER [0] RW Enable filter on GPIO wakeup sources enabled by the GPIO_PnWAKE regis- ters. |
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