EM342-RTR datasheet(83/143 Pages) SILABS

83 / 143 page

EM342

Rev 1.0

8.4.7. Registers

Refer to " " on page 73 (in “ ” ) for a description of the SCx_DATA register.

SC1_UARTSTAT: Address: 0x4000C848 Reset: 0x40

Bit

Name

Bit

Name

Bit

Name

Bit

Name

SC_

UARTTXIDLE

SC_

UARTPARERR

SC_

UARTFRMERR

SC_

UARTRXOVF

SC_

UARTTXFREE

SC_

UARTRXVAL

SC_

UARTCTS

Bitname

Bitfield Access

Description

SC_UARTTXIDLE

[6]

This bit is set when both the transmit FIFO and the transmit serializer are empty.

SC_UARTPARERR

[5]

This bit is set when the byte in the data register was received with a parity error. This

bit is updated when the data register is read, and is cleared if the receive FIFO is

empty.

SC_UARTFRMERR

[4]

This bit is set when the byte in the data register was received with a frame error. This

bit is updated when the data register is read, and is cleared if the receive FIFO is

empty.

SC_UARTRXOVF

[3]

This bit is set when the receive FIFO has been overrun. This occurs if a byte is

received when the receive FIFO is full. This bit is cleared by reading the data regis-

ter.

SC_UARTTXFREE

[2]

This bit is set when the transmit FIFO has space for at least one byte.

SC_UARTRXVAL

[1]

This bit is set when the receive FIFO contains at least one byte.

SC_UARTCTS

[0]

This bit shows the logical state (not voltage level) of the nCTS input:

0: nCTS is deasserted (pin is high, 'XOFF', RS232 negative voltage); the UART is

inhibited from starting to transmit a byte.

1: nCTS is asserted (pin is low, 'XON', RS232 positive voltage); the UART may

transmit.

EM342-RTR Datasheet(PDF) 83 Page - Silicon Laboratories

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