EM342-RTR datasheet(37/143 Pages) SILABS

37 / 143 page

EM342

Rev 1.0

6.2.1.8. Deep Sleep Reset

The Power Management module informs the Reset Generation module of entry into and exit from the deep sleep

states. The deep sleep reset is applied in the following states: before entry into deep sleep, while removing power

from the memory and core domain, while in deep sleep, while waking from deep sleep, and while reapplying power

until reliable power levels have been detect by POR LV.

The Power Management module allows a special emulated deep sleep state that retains memory and core domain

power while in deep sleep.

6.2.2. Reset Recording

The EM342 records the last reset condition that generated a restart to the system. The reset conditions recorded

are as follows:



POR HV

always-on domain power supply failure



POR LV

core domain (POR LVcore) or memory domain (POR LVmem) power supply failure



nRESET

pin reset asserted



watchdog

watchdog timer expired



SYSRESETREQ

software reset by SYSERSETREQ from ARM® CortexTM-M3 CPU



deep sleep wakeup

wake-up from deep sleep



option byte error

error check failed when reading option bytes from flash



Note: While CPU Lockup is shown as a reset condition in software, CPU Lockup is not specifically a reset event. CPU Lockup

is set to indicate that the CPU entered an unrecoverable exception. Execution stops but a reset is not applied. This is so

that a debugger can interpret the cause of the error. Silicon Labs recommends that in a live application (in other words,

no debugger attached) the watchdog be enabled by default so that the EM342 can be restarted.

6.2.3. Reset Generation Module

The Reset Generation module responds to reset sources and generates the following reset signals:



PORESET

Reset of the ARM® CortexTM-M3 CPU and ARM® CortexTM-M3 System Debug

components (Flash Patch and Breakpoint, Data Watchpoint and Trace,

Instrumentation Trace Macrocell, Nested Vectored Interrupt Controller). ARM

defines PORESET as the region that is reset when power is applied.



SYSRESET

Reset of the ARM® CortexTM-M3 CPU without resetting the Core Debug and

System Debug components, so that a live system can be reset without disturbing

the debug configuration.



DAPRESET

Reset to the SWJ’s AHB Access Port (AHB-AP)



PRESETHV

Peripheral reset for always-on power domain, for peripherals that are required to

retain their configuration across a deep sleep cycle



PRESETLV

Peripheral reset for core power domain, for peripherals that are not required to

retain their configuration across a deep sleep cycle

EM342-RTR Datasheet(PDF) 37 Page - Silicon Laboratories

EM342-RTR Datasheet(HTML) 37 Page - Silicon Laboratories

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