EM342-RTR datasheet(43/143 Pages) SILABS

43 / 143 page

EM342

Rev 1.0

6.4. System Timers

6.4.1. Watchdog Timer

The EM342 integrates a watchdog timer which can be enabled to provide protection against software crashes and

ARM® CortexTM-M3 CPU lockup. By default, it is disabled at power up of the always-on power domain. The

watchdog timer uses the calibrated 1 kHz clock (CLK1K) as its reference and provides a nominal 2.048 s timeout.

A low water mark interrupt occurs at 1.792 s and triggers an NMI to the ARM® CortexTM-M3 NVIC as an early

warning. When the watchdog is enabled, the timer must be periodically reset before it expires. The watchdog timer

is paused when the debugger halts the ARM® CortexTM-M3. Additionally, the Ember software that implements

deep sleep functionality disables the watchdog when entering deep sleep and restores the watchdog, if it was

enabled, when exiting deep sleep.

Ember software provides an API for enabling, resetting, and disabling the watchdog timer.

6.4.2. Sleep Timer

The EM342 integrates a 32-bit timer dedicated to system timing and waking from sleep at specific times. The sleep

timer can use either the calibrated 1 kHz reference (CLK1K), or the 32 kHz crystal clock (CLK32K). The default

clock source is the internal 1 kHz clock.

The sleep timer has a prescaler, a divider of the form 2^N, where N can be programmed from 1 to 2^15. This

divider allows for very long periods of sleep to be timed. Ember software’s default configuration is to use the

prescaler to always produce a 1024 Hz sleep timer tick. The timer provides two compare outputs and wrap

detection, all of which can be used to generate an interrupt or a wake up event.

While it is possible to do so, by default the sleep timer is not paused when the debugger halts the ARM® CortexTM-

M3. Silicon Labs does not advise pausing the sleep timer when the debugger halts the CPU.

To save current during deep sleep, the low-frequency internal RC oscillator (OSCRC) can be turned off. If OSCRC

is turned off during deep sleep and a low-frequency 32.768 kHz crystal oscillator is not being used, then the sleep

timer will not operate during deep sleep and sleep timer wake events cannot be used to wake up the EM342.

Ember software provides the system timer software API for interacting with the sleep timer as well as using the

sleep timer and RC oscillator during deep sleep.

Note: Because the system timer software module handles all interactions with the sleep timer, the module will return the cor-

rect value in all situations. In the situation where the chip performs a deep sleep that maintains the system time and is

woken up from an external event (that is, not a sleep timer event), the deep sleep module in the Ember software delays

until the next sleep timer clock tick (up to 1 ms) to guarantee that the sleep timer updates correctly.

6.4.3. Event Timer

The SysTick timer is an ARM® standard system timer in the NVIC. The SysTick timer can be clocked from either

the FCLK (the clock going into the CPU) or the Sleep Timer clock. FCLK is either the SYSCLK or PCLK as selected

by CPU_CLKSEL register (see “6.3.5. Clock Switching” ).

EM342-RTR Datasheet(PDF) 43 Page - Silicon Laboratories