EM342-RTR datasheet(44/143 Pages) SILABS

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EM342

Rev 1.0

6.5. Power Management

The EM342’s power management system is designed to achieve the lowest deep sleep current consumption

possible while still providing flexible wakeup sources, timer activity, and debugger operation. The EM342 has four

main sleep modes:



Idle Sleep: Puts the CPU into an idle state where execution is suspended until any interrupt occurs. All

power domains remain fully powered and nothing is reset.



Deep Sleep 1: The primary deep sleep state. In this state, the core power domain is fully powered down

and the sleep timer is active.



Deep Sleep 2: The same as Deep Sleep 1 except that the sleep timer is inactive to save power. In this

mode the sleep timer cannot wake up the EM342.



Deep Sleep 0 (also known as Emulated Deep Sleep): The chip emulates a true deep sleep without

powering down the core domain. Instead, the core domain remains powered and all peripherals except the

system debug components (ITM, DWT, FPB, NVIC) are held in reset. The purpose of this sleep state is to

allow EM342 software to perform a deep sleep cycle while maintaining debug configuration such as

breakpoints.



CSYSPWRUPREQ, CDBGPWRUPREQ, and the corresponding CSYSPWRUPACK and

CDBGPWRUPACK are bits in the debug port’s CTRL/STAT register in the SWJ. For further information on

these bits and the operation of the SWJ-DP please refer to the ARM Debug Interface v5 Architecture

Specification (ARM IHI 0031A).

For further power savings when not in deep sleep, the Serial Controller1 peripheral can be individually disabled

through the PERIPHERAL_DISABLE register. Disabling a peripheral saves power by stopping the clock feeding

that peripheral. A peripheral should only be disabled through the PERIPHERAL_DISABLE register when the

peripheral is idle and disabled through the peripheral's own configuration registers, otherwise undefined behavior

may occur. When a peripheral is disabled through the PERIPHERAL_DISABLE register, all registers associated

with that peripheral ignore all subsequent writes, and subsequent reads return the value seen in the register at the

moment the peripheral is disabled.

6.5.1. Wake Sources

When in deep sleep the EM342 can be returned to the running state in a number of ways, and the wake sources

are split depending on deep sleep 1 or deep sleep 2.

The following wake sources are available in both deep sleep 1 and 2.



Wake on GPIO activity: Wake due to change of state on any GPIO.



Wake on serial controller 1: Wake due to a change of state on GPIO Pin PB2.



Wake on IRQD: Wake due to a change of state on IRQD. Since IRQD can be configured to point to any

GPIO, this wake source is another means of waking on any GPIO activity.



Wake on setting of CDBGPWRUPREQ: Wake due to setting the CDBGPWRUPREQ bit in the debug port

in the SWJ.



Wake on setting of CSYSPWRUPREQ: Wake due to setting the CSYSPWRUPREQ bit in the debug port in

the SWJ.

The following sources are only available in deep sleep 1 since the sleep timer is not active in deep sleep 2.



Wake on sleep timer compare A.



Wake on sleep timer compare B.



Wake on sleep timer wrap.

The following source is only available in deep sleep 0 since the SWJ is required to write a memory mapped register

to set this wake source and the SWJ only has access to some registers in deep sleep 0.



Wake on write to the WAKE_CORE register bit.

The Wakeup Recording module monitors all possible wakeup sources. More than one wakeup source may be

recorded because events are continually being recorded (not just in deep-sleep) and another event may happen

between the first wake event and when the EM342 wakes up.

EM342-RTR Datasheet(PDF) 44 Page - Silicon Laboratories

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