EM342-RTR datasheet(101/143 Pages) SILABS

101 / 143 page

EM342

Rev 1.0

101

Table 9.1. NVIC Exception Table

Exception

Position

Description

—

Stack top is loaded from first entry of vector table on reset.

Reset

Invoked on power up and warm reset. On first instruction, drops to lowest prior-

ity (Thread mode). Asynchronous.

NMI

Cannot be stopped or preempted by any exception but reset. Asynchronous.

Hard Fault

All classes of fault, when the fault cannot activate because of priority or the

Configurable Fault handler has been disabled. Synchronous.

Memory Fault

MPU mismatch, including access violation and no match. Synchronous.

Bus Fault

Pre-fetch, memory access, and other address/memory-related faults. Synchro-

nous when precise and asynchronous when imprecise.

Usage Fault

Usage fault, such as “undefined instruction executed” or “illegal state transition

attempt”. Synchronous.

—

7–10

Reserved.

SVCall

System service call with SVC instruction. Synchronous.

Debug Monitor

Debug monitor, when not halting. Synchronous, but only active when enabled.

It does not activate if lower priority than the current activation.

—

Reserved.

PendSV

Pendable request for system service. Asynchronous and only pended by soft-

ware.

SysTick

System tick timer has fired. Asynchronous.

—

Reserved.

—

Reserved.

Management

Management peripheral interrupt.

Baseband

Baseband peripheral interrupt.

Sleep Timer

Sleep Timer peripheral interrupt.

Serial Controller 1

Serial Controller 1 peripheral interrupt.

—

Reserved.

Security

Security peripheral interrupt.

MAC Timer

MAC Timer peripheral interrupt.

MAC Transmit

MAC Transmit peripheral interrupt.

MAC Receive

MAC Receive peripheral interrupt.

—

Reserved.

IRQA

IRQA peripheral interrupt.

—

Reserved

IRQC

IRQC peripheral interrupt.

IRQD

IRQD peripheral interrupt.

Debug

Debug peripheral interrupt.

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