EM342-RTR datasheet(105/143 Pages) SILABS

105 / 143 page

EM342

Rev 1.0

105

level interrupt, which then triggers the NMI.

2. Watchdog low water mark: If the EM342's watchdog is active and the watchdog counter has not been reset

for nominally 1.792 s, the watchdog triggers the WATCHDOG_INT second-level interrupt, which then

triggers the NMI.

9.4. Faults

Four of the exceptions in the NVIC are faults: Hard Fault, Memory Fault, Bus Fault, and Usage Fault. Of these,

three (Hard Fault, Memory Fault, and Usage Fault) are standard ARM® CortexTM-M3 exceptions.

The Bus Fault, though, is derived from EM342-specific sources. The Bus Fault sources are recorded in the

SCS_AFSR register. Note that it is possible for one access to set multiple SCS_AFSR bits. Also note that MPU

configurations could prevent most of these bus fault accesses from occurring, with the advantage that illegal writes

are made precise faults. The four bus faults are:



WRONGSIZE—Generated by an 8-bit or 16-bit read or write of an APB peripheral register. This fault can

also result from an unaligned 32-bit access.



PROTECTED—Generated by a user mode (unprivileged) write to a system APB or AHB peripheral or

protected RAM (see "5.2.2.3. RAM Memory Protection" on page 31).



RESERVED—Generated by a read or write to an address within an APB peripheral's 4 kB block range, but

the address is above the last physical register in that block range. Also generated by a read or write to an

address above the top of RAM or flash.



MISSED—Generated by a second SCS_AFSR fault. In practice, this bit is not seen since a second fault

also generates a hard fault, and the hard fault preempts the bus fault.

EM342-RTR Datasheet(PDF) 105 Page - Silicon Laboratories